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https://github.com/YosysHQ/yosys
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autoname: selection determines what gets renamed, not the name it gets renamed to
This commit is contained in:
Emil J. Tywoniak
parent
fb0bb160ad
commit
8565451ef9
2 changed files with 60 additions and 27 deletions
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@ -79,6 +79,7 @@ struct node {
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unsigned int fanout = 0;
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bool is_public = false;
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bool renameable = false;
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bool selected = false;
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size_t name_length = 0;
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// Node index from which we want to construct the rename
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@ -89,6 +90,8 @@ struct node {
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string suffix;
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// Is this name final?
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bool decided = false;
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const IdString& name() const { return cell ? cell->name : wire->name; }
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};
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// Decides the order of exploring neighbors
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@ -106,7 +109,7 @@ struct ModuleAutonamer
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// Cells in module order, then wires in the order that they're seen from cells.
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// The index doubles as the tie-break between equally good
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// proposals for different nodes.
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// proposals for different nodes
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vector<node> nodes;
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vector<int> decided;
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std::priority_queue<queue_item, std::vector<queue_item>, std::greater<>> queue;
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@ -116,9 +119,9 @@ struct ModuleAutonamer
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void build_adjacency()
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{
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auto selected = module->selected_cells();
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// Arbitrary. Kinda just for passing tests without modifying them.
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for (auto cell : selected | std::views::reverse)
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vector<Cell*> cells(module->cells().begin(), module->cells().end());
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// Arbitrary. Kinda just for passing tests without modifying them
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for (auto cell : cells | std::views::reverse)
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nodes.emplace_back().cell = cell;
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int ncells = GetSize(nodes);
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@ -153,23 +156,25 @@ struct ModuleAutonamer
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}
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}
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// Resolve selection before renaming
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for (auto &nd : nodes) {
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IdString name = nd.cell ? nd.cell->name : nd.wire->name;
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IdString name = nd.name();
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nd.selected = nd.cell ? module->selected(nd.cell) : module->selected(nd.wire);
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nd.is_public = (name[0] != '$');
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nd.renameable = !nd.is_public && (nd.cell || nd.wire->port_id == 0);
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if (nd.is_public)
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nd.name_length = name.str().size();
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}
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// Only possible once every fanout is known.
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// Only possible once every fanout is known
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for (auto &nd : nodes)
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for (auto &edge : nd.edges)
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edge.score = edge.cell_is_output ? 0 : nodes[edge.wire].fanout;
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}
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void offer(int from, int n, const Edge &edge, int edge_pos)
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void offer(int from, int to, const Edge &edge, int edge_pos)
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{
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node &nd = nodes[n];
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node &nd = nodes[to];
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if (!nd.renameable || nd.decided)
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return;
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string suffix = nd.cell
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@ -182,7 +187,7 @@ struct ModuleAutonamer
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nd.from_node = from;
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nd.name_length = c.length;
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nd.suffix = std::move(suffix);
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queue.push(queue_item{c.score, c.length, n});
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queue.push(queue_item{c.score, c.length, to});
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}
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// Expand a public (or newly decided) node. The name it lends
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@ -214,15 +219,23 @@ struct ModuleAutonamer
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}
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}
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// The source neighbour is decided before this node, so commit() reaches it
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// first and its name is already final -- uniquify() suffix and all.
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void append_name(int n, string &out)
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{
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const node &nd = nodes[n];
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if (nd.is_public || nd.selected)
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return nd.name().append_to(&out);
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append_name(nd.from_node, out);
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out += nd.suffix;
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}
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void commit(int n)
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{
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node &nd = nodes[n];
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const node &src = nodes[nd.from_node];
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if (!nd.selected)
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return;
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string full;
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full.reserve(nd.name_length);
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(src.cell ? src.cell->name : src.wire->name).append_to(&full);
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append_name(nd.from_node, full);
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full += nd.suffix;
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IdString name = module->uniquify(IdString(full));
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if (nd.cell) {
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@ -78,12 +78,21 @@ module \top
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end
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end
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EOT
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design -save fanout_test
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logger -expect log "Rename cell .name in top to bcd_.and_B" 1
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logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# a selection only limits what gets renamed, never the name that gets picked:
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# \a's fanout still counts $name2, even though it isn't selected
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design -load fanout_test
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logger -expect log "Rename cell .name in top to bcd_.and_B" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname c:$name
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logger -check-expected
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# names are unique
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design -reset
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read_rtlil <<EOT
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@ -177,30 +186,41 @@ end
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EOT
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design -save order_test
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# don't rename prematurely (some objects should be named after $name2)
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# wires are named for being cell outputs
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logger -expect log "Rename wire .d in top to or_Y" 1
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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logger -expect log "Renamed 4 objects" 1
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debug autoname t:$or
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logger -check-expected
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# $name gets shortest name (otherwise bcd_$__unknown_B)
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logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
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# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# don't rename prematurely (some objects should be named after $name2)
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design -load order_test
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# $c gets shortest name, since the cell driving it doesn't have known port
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# directions (otherwise a_$__unknown_A_Y)
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 6 objects" 1
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debug autoname
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logger -check-expected
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# Only selected objects are renamed, but each one gets exactly the name the
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# unrestricted run above gave it, whatever the selection.
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design -load order_test
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname t:$or
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logger -check-expected
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design -load order_test
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logger -expect log "Rename wire .d in top to or_Y" 1
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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logger -expect log "Renamed 3 objects" 1
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debug autoname w:*
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logger -check-expected
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# $name3 is named after a chain of objects that all keep their $-names
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design -load order_test
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname c:$name3
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logger -check-expected
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