3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-14 09:55:37 +00:00
yosys/tests/various
2026-06-09 16:22:51 +03:00
..
dynamic_part_select
.gitignore Merge remote-tracking branch 'upstream/main' into silimate 2026-06-09 16:22:51 +03:00
abc9.v
abc9.ys
abstract_init.ys abstract: test -slice from:to for -init 2025-02-25 00:22:14 +01:00
abstract_initstates.ys abstract: Add -initstates option 2025-08-12 15:37:12 +02:00
abstract_state.ys abstract: test -slice for all modes, -rtlilslice for -init 2025-02-25 00:18:16 +01:00
abstract_value.ys abstract: test -slice for all modes, -rtlilslice for -init 2025-02-25 00:18:16 +01:00
aiger2.ys kernel: Rewrite bufNormalize 2025-09-17 13:56:46 +02:00
aiger_dff.ys
async.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys autoname.ys: Extra check for rename order 2025-09-26 11:36:23 +12:00
blackbox_wb.ys
box_derive.ys box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
bufnorm_opt_clean.ys bufnorm: Refactor and fix incremental bufNormalize 2025-09-29 08:21:28 +02:00
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys
bug2014.ys
bug3462.ys
bug3515.v tests: Add bug3515 2025-11-25 07:04:34 +13:00
bug3515.ys tests: Tidy up bug3515 2025-11-25 07:35:19 +13:00
bug3879.ys extract_fa: Add test case 2025-01-30 18:45:06 +01:00
bug4082.ys
bug4865.ys ice40_dsp: fix test 2025-03-26 15:13:05 +02:00
bug4909.ys splitcells: add tests 2025-03-10 19:41:22 +02:00
cellarray_array_connections.ys
celledges_shift.ys
check.ys More minor cleanup 2025-09-28 07:19:53 -07:00
check_2.ys Final cleanup 2025-02-14 10:18:13 -08:00
check_3.ys Final cleanup 2025-02-14 10:18:13 -08:00
check_4.ys fixes for the yosys test 2025-03-27 17:19:08 -07:00
chformal_check.ys chformal: Add -assert2cover option 2025-06-14 10:54:23 +12:00
chformal_coverenable.ys
chparam.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sv
const_arg_loop.sv
const_arg_loop.ys Merge upstream in 2025-09-09 05:50:48 -07:00
const_func.sv
const_func.ys Merge upstream in 2025-09-09 05:50:48 -07:00
const_func_block_var.v
const_func_block_var.ys
const_shift_empty_arg.ys Fix segfault from shift with 0-width signed arg. 2026-02-12 22:03:42 -06:00
constant_drive_conflict.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys Merge upstream in 2025-09-09 05:50:48 -07:00
cutpoint_blackbox.ys Fixups 2025-09-29 03:49:44 -07:00
cutpoint_whole.ys cutpoint: Re-add whole module optimization 2025-05-06 09:57:34 +12:00
debugon.ys Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
deminout_unused.ys
design.ys
design1.ys
design2.ys
design_equal_fail.ys Implement design_equal command 2025-12-21 21:47:40 +00:00
design_equal_pass.ys Implement design_equal command 2025-12-21 21:47:40 +00:00
dynamic_part_select.ys
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_assume.ys tests: Add equiv_induct to equiv_assume.ys 2025-08-06 15:13:04 +12:00
equiv_make_make_assert.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys
exec.ys
ezcmdline_dummy_solver Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
ezcmdline_plugin.cc Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
ezcmdline_plugin.sh Update CI scripts for CMake 2026-06-03 08:58:11 +00:00
fib.v
fib.ys
fib_tern.v
fib_tern.ys
formalff_declockgate.ys formalff: Fix -declockgate test and missing emit for memories 2025-04-18 18:57:59 +02:00
fsm-arst.ys typo 2025-11-14 13:34:58 +02:00
func_port_implied_dir.sv
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys
generate_mk.py Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
hierarchy_defer.ys
hierarchy_generate.ys
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys
json_param_defaults.v Add tests 2026-02-11 08:10:57 -08:00
json_param_defaults.ys Don't dump params by default 2026-02-11 08:33:39 -08:00
json_scopeinfo.ys Undo flatten -scopeinfo to -noscopeinfo 2025-04-22 16:32:22 -07:00
keep_hierarchy.ys
lcov.gold print summary of line coverage to log 2025-07-16 13:40:07 +02:00
lcov.v update test to use suggested selection for assertions 2025-07-01 11:46:27 +02:00
lcov.ys update test to use suggested selection for assertions 2025-07-01 11:46:27 +02:00
logger_cmd_error.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
logger_error.ys
logger_fail.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxpack.v
muxpack.ys
muxpack_wide_y.ys Regression test for #5765 2026-03-30 08:59:28 -07:00
opt_andor_pmux.v Smallfix 2026-05-27 04:36:45 -07:00
opt_andor_pmux.ys opt_andor_pmux pass 2026-05-27 00:11:54 -07:00
param_struct.ys Merge upstream in 2025-09-09 05:50:48 -07:00
peepopt.ys peepopt: add shiftpow2 pattern 2026-05-31 02:01:32 +02:00
peepopt_formal.ys
plugin.cc
plugin.sh Update CI scripts for CMake 2026-06-03 08:58:11 +00:00
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v
port_sign_extend.ys
primitives.ys
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys
rename_scramble_name.ys
rename_unescape.ys rename.cc: Fixup ports after -unescape 2025-08-15 10:48:32 +12:00
rename_wire_move_to_cell.ys rename: add -move-to-cell option in -wire mode 2025-08-13 11:11:52 +02:00
rtlil_signed_attribute.ys
rtlil_z_bits.ys
scopeinfo.ys Undo flatten -scopeinfo to -noscopeinfo 2025-04-22 16:32:22 -07:00
scratchpad.ys
script.ys
setundef.sv
setundef.ys
setundef_selection.ys changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
setundef_selection_ff.il setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
setundef_selection_undriven.v changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
sformatf.ys
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v
specify.ys specify: fix test 2026-02-03 18:40:32 +01:00
splitcells.ys Fix offset in splitcells 2026-04-09 16:20:26 -07:00
splitnets.ys splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
src.ys
sta.ys
stat.ys updated testcase 2025-08-16 09:32:08 +02:00
struct_access.sv
struct_access.ys
sub.v
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
svalways.sh proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
tcl_apis.tcl
tcl_apis.v
tcl_apis.ys
test_splitnets.tcl splitnets new options 2025-02-19 09:43:53 -08:00
test_splitnets.v splitnets new options 2025-02-19 09:43:53 -08:00
test_splitnets.ys splitnets new options 2025-02-19 09:43:53 -08:00
timeest.ys timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
wrapcell.ys opt_clean was removing the unused bits annotation 2025-01-16 19:48:31 -08:00
wreduce.ys
wreduce2.ys wreduce: Optimize signedness when possible 2024-12-16 12:57:08 +01:00
write_gzip.ys
xaiger.ys