Akash Levy
a121255f47
Merge branch 'YosysHQ:main' into main
2026-01-13 11:28:34 -08:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log
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read_verilog: remove log I left behind by accident
2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire
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Add autowires in genblk/for expension
2026-01-13 16:40:22 +01:00
Akash Levy
e332ba807d
Merge branch 'YosysHQ:main' into main
2026-01-07 12:40:39 -08:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz
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Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
2026-01-06 20:07:31 +01:00
Akash Levy
1941e8f042
Bump yosys and abc to latest
2025-12-25 03:46:16 -05:00
N. Engelhardt
d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties
2025-12-22 16:54:43 +01:00
Robert O'Callahan
46cb05c471
Pass IdString by value instead of by const reference.
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When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
2025-12-22 01:52:59 +00:00
Robert O'Callahan
ddd6a16ee0
Add -legalize option to read_rtlil
2025-12-21 21:47:48 +00:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Yannick Lamarre
9814f9dc4f
Add autowires in genblk/for expension
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Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
2025-12-10 14:43:42 +01:00
Akash Levy
c2d8a4e43f
Merge branch 'YosysHQ:main' into main
2025-12-01 23:54:18 -05:00
Emil J
9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops
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read_liberty: support loopy retention cells
2025-12-01 22:50:20 +01:00
Akash Levy
4a25f63699
Merge from upstream
2025-11-29 11:53:48 -05:00
Robert O'Callahan
8f0ecce53f
Forbid creating IdStrings and incrementing autoidx during multithreaded phases, and add dynamic checks for that
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We could make it safe to increment autoidx during multithreaded passes, but that's
actually undesirable because it would lead to nondeterminism. If/when we need new
IDs during parallel passes, we'll have to figure out how to allocate them in a
deterministic way, and that will depend on the details of what the pass does.
So don't try to tackle that now.
2025-11-25 21:57:46 +00:00
Akash Levy
71ba176b50
Merge branch 'YosysHQ:main' into main
2025-11-24 14:04:13 -05:00
Mike Inouye
f098352ae6
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
Emil J. Tywoniak
d5c1cd8fc0
read_liberty: support loopy retention cells
2025-11-20 13:21:32 +01:00
Emil J. Tywoniak
302643330c
read_liberty: add cell context to more errors, remove log_id
2025-11-20 13:21:28 +01:00
Akash Levy
e21324d609
Merge from upstream
2025-11-11 22:52:11 -08:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
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Handle unsized params
2025-11-12 07:14:44 +13:00
Emil J. Tywoniak
8f53d21ea7
simplify: refactor specific package import
2025-11-10 14:26:10 +01:00
Rahul Bhagwat
54e5eb1c3c
no use vector
2025-11-08 23:16:52 +05:30
Rahul Bhagwat
224109151d
add specific package imports and tests
2025-11-08 23:05:10 +05:30
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
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In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
Krystine Sherwin
a5cc905184
simplify.cc: Fix unsized const in params
2025-11-07 15:52:24 +13:00
Akash Levy
11731c91f4
Merge from upstream
2025-11-04 22:20:34 -08:00
KrystalDelusion
52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor
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Refactor getting dirs and filenames from paths to files
2025-11-05 09:12:54 +13:00
Akash Levy
76c12f8f8c
Merge branch 'YosysHQ:main' into main
2025-11-03 13:38:04 -05:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11
2025-10-26 02:39:43 +03:00
Robert O'Callahan
25aafab86b
Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec
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Don't stop parsing sigspec after a {} group.
2025-10-15 17:31:11 +02:00
Robert O'Callahan
e099a7d34a
Don't stop parsing sigspec after a {} group.
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Resolves #5424
2025-10-14 21:18:58 +00:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
Miodrag Milanovic
2f8f421dee
verifix: fix bits() deprecation warnings
2025-10-13 09:47:18 +02:00
Akash Levy
54653fc82c
Reenable Verific opt and comment out clock enable muxing
2025-10-12 07:52:32 -07:00
Akash Levy
6993fc2540
Flush during import
2025-10-12 07:52:12 -07:00
Emil J
a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser
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Rewrite the RTLIL parser for efficiency
2025-10-08 14:52:37 +02:00
N. Engelhardt
0b6adf832b
verific: print source location of problematic object on import error (if available)
2025-10-03 12:57:49 +02:00
Akash Levy
623c54d513
Only do SFCU if has VHDL
2025-10-02 06:02:39 -07:00
Robert O'Callahan
915ad949f9
Limit the maximum size of parsed RTLIL constants to 1 Gb.
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Without this check it's trivially easy to crash Yosys with a tiny RTLIL input
by specifying a constant with very large width. Fuzz testers love hitting this
over and over again.
2025-10-01 02:17:22 +00:00
Robert O'Callahan
ac4cb5e460
Implement a handwritten recursive-descent RTLIL parser with minimal copying
2025-10-01 02:17:22 +00:00
Akash Levy
16215b8786
Merge upstream
2025-09-29 20:58:56 -07:00
ShinyKate
30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff
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read_blif: Represent sequential elements with gate cells
2025-09-29 08:21:16 -05:00
Akash Levy
507d43a9b8
Fixups
2025-09-28 06:16:07 -07:00
Akash Levy
652a9a63b2
Update to latest and fix all disabled tests
2025-09-28 01:33:08 -07:00
