Akash Levy
e8d27892f0
Merge pull request #96 from Silimate/fanoutbuf_src_attr
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Changed fanoutbuf.cc to include src attributes on buffers connected t…
2026-01-28 17:50:46 -08:00
AdvaySingh1
3ce57442de
Changed fanoutbuf.cc to include src attributes on buffers connected to input and output wires
2026-01-28 15:33:13 -08:00
Akash Levy
b356c9ac3e
Add unistd header for Linux
2026-01-26 23:12:02 -08:00
Akash Levy
26f5ff3d74
Merge from upstream
2026-01-26 22:16:11 -08:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl
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Add `linux_perf` command to turn Linux perf recording on and off.
2026-01-26 19:32:55 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates
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Don't update `used_signals` for retained wires in `rmunused_module_signals`.
2026-01-26 15:47:25 +01:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
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These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word
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lut2mux: add -word option
2026-01-23 17:24:41 +01:00
Robert O'Callahan
4f53612725
Add linux_perf command to turn Linux perf recording on and off.
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This is extremely useful for profiling specific passes.
2026-01-23 01:44:57 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
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abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
Akash Levy
5a6dffeecd
Silimate mods to upstream opt_balance_tree pass
2026-01-21 23:34:34 -08:00
Stan Lee
a52689a1fa
Merge branch 'main' into main
2026-01-21 15:46:06 -08:00
Stan Lee
99cf75531f
merge
2026-01-21 15:43:25 -08:00
Stan Lee
f026cebaf6
address comments
2026-01-21 15:16:45 -08:00
Akash Levy
947139aca1
Remove opt_balance_tree from silimate (now in opt)
2026-01-21 15:15:21 -08:00
Akash Levy
b11037e6c6
Merge remote-tracking branch 'upstream/main'
2026-01-21 15:13:57 -08:00
Stan Lee
f14eb4a7bb
only check reg cells
2026-01-21 15:13:55 -08:00
Stan Lee
269b70c0f9
compiles
2026-01-21 12:32:38 -08:00
Stan Lee
0018037c16
minor changes
2026-01-21 12:25:28 -08:00
Stan Lee
e824c8e0d6
ready for review
2026-01-21 09:00:46 -08:00
Stan Lee
31e32af4a8
greptile
2026-01-21 08:54:43 -08:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
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Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
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Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
Stan Lee
d2e8f9b8a8
first round fixes
2026-01-20 21:45:13 -08:00
Stan Lee
29061d3051
leave no room for err
2026-01-20 15:55:05 -08:00
Stan Lee
45bd3f4515
change splitcells pass to remove some bracket from register names in blast mode
2026-01-20 15:50:43 -08:00
Stan Lee
60a81a2676
reg rename pass reads from vcd for original widths
2026-01-20 15:35:13 -08:00
Stan Lee
a5106da733
line reduction
2026-01-20 11:56:57 -08:00
Stan Lee
0ea4bb8a2d
comment
2026-01-20 11:55:54 -08:00
Stan Lee
80364c608e
significantly cleaner
2026-01-20 11:29:56 -08:00
Martin Povišer
90673cb0a2
techmap: Use -icells mode of frontend instead of type fixup
2026-01-19 16:49:49 -08:00
Stan Lee
c471014878
slightly cleaner
2026-01-19 12:58:36 -08:00
Stan Lee
6303eed1b4
works hierarchy
2026-01-19 12:22:22 -08:00
Stan Lee
186fc15f8f
passes simple test
2026-01-19 12:10:48 -08:00
Stan Lee
e678e2a0c3
every step except wire connecting
2026-01-19 11:20:11 -08:00
Stan Lee
15026033a3
annotate original register width
2026-01-19 11:19:41 -08:00
Emil J. Tywoniak
c3f36afe7f
opt_balance_tree: mark experimental
2026-01-19 12:01:25 +01:00
Robert O'Callahan
28c199fbbd
Fix warning about unused variable in dffunmap.
2026-01-19 03:25:09 +00:00
Akash Levy
7792f0644a
Merge branch 'YosysHQ:main' into main
2026-01-18 17:17:45 -08:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err
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Improve error handling in sim
2026-01-19 09:51:12 +13:00
Stan Lee
4a1af73ec0
activity pass and a vcd writer bug fix
2026-01-16 16:32:04 -08:00
Natalia
ed64df737b
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
Akash Levy
33ddae41c3
Remove lut2bmux from silimate after upstreaming
2026-01-14 20:24:26 -08:00
Natalia
305b6c81d7
Refine width check to allow Y_WIDTH >= natural width
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Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).
This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
Natalia
60ac3670cb
Fix truncation issue in opt_balance_tree pass
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Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.
For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)
Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
2026-01-14 13:14:56 -08:00
Natalia Kokoromyti
6aef8ea8ab
Add missing <deque> include for MSVC compatibility
2026-01-13 15:31:46 -08:00
nataliakokoromyti
8a596f330a
Update lut2mux.cc
2026-01-13 15:02:17 -08:00
nataliakokoromyti
40f9e235de
Update lut2mux.cc
2026-01-13 14:45:46 -08:00
nataliakokoromyti
6a93a94d9f
fix line
2026-01-13 14:44:51 -08:00
