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Merge from upstream

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This commit is contained in:
Akash Levy 2026-01-26 22:16:11 -08:00
commit 26f5ff3d74
20 changed files with 1231 additions and 38 deletions
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1
passes/cmds/Makefile.inc
View file

@ -37,6 +37,7 @@ OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
OBJS += passes/cmds/ltp.o
OBJS += passes/cmds/linux_perf.o
ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/cmds/bugpoint.o
endif

96
passes/cmds/linux_perf.cc Normal file
View file

@ -0,0 +1,96 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2014 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/log_help.h"
#include <fcntl.h>
#include <stdlib.h>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#ifdef __linux__
struct LinuxPerf : public Pass {
LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { }
void help() override
{
log("This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs.\n");
log("\n");
log("Example shell command line:\n");
log("mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n");
log("YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n");
log(" perf record --latency --delay=-1 \\\n");
log(" --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys -dt -p \\\n");
log(" \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n");
log("\n");
log(" linux_perf on\n");
log("\n");
log("Start perf recording. YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs.\n");
log("\n");
log(" linux_perf off\n");
log("\n");
log("Stop perf recording.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *) override
{
if (args.size() > 2)
cmd_error(args, 2, "Unexpected argument.");
std::string_view ctl_msg;
if (args.size() == 2) {
if (args[1] == "on")
ctl_msg = "enable\n";
else if (args[1] == "off")
ctl_msg = "disable\n";
else
cmd_error(args, 1, "Unexpected argument.");
}
const char *ctl_fifo = std::getenv("YOSYS_PERF_CTL");
if (!ctl_fifo)
log_error("YOSYS_PERF_CTL environment variable not set.");
const char *ack_fifo = std::getenv("YOSYS_PERF_ACK");
if (!ack_fifo)
log_error("YOSYS_PERF_ACK environment variable not set.");
int ctl_fd = open(ctl_fifo, O_WRONLY);
if (ctl_fd < 0)
log_error("Failed to open YOSYS_PERF_CTL.");
int ack_fd = open(ack_fifo, O_RDONLY);
if (ack_fd < 0)
log_error("Failed to open YOSYS_PERF_ACK.");
int result = write(ctl_fd, ctl_msg.data(), ctl_msg.size());
if (result != static_cast<int>(ctl_msg.size()))
log_error("Failed to write to YOSYS_PERF_CTL.");
char buffer[64];
result = read(ack_fd, buffer, sizeof(buffer));
close(ctl_fd);
close(ack_fd);
if (result <= 0)
log_error("Failed to read from YOSYS_PERF_ACK.");
if (strcmp(buffer, "ack\n") != 0)
log_error("YOSYS_PERF_ACK did not return 'ack'.");
}
} LinuxPerf;
#endif
PRIVATE_NAMESPACE_END

2
passes/opt/opt_clean.cc
View file

@ -467,8 +467,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool unused
wire->attributes.erase(ID::init);
else
wire->attributes.at(ID::init) = initval;
used_signals.add(new_conn.first);
used_signals.add(new_conn.second);
module->connect(new_conn);
}

6
passes/techmap/abc.cc
View file

@ -1149,6 +1149,12 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) {
// Ignore any leftover output, there should only be a prompt perhaps
return true;
}
// If ABC aborted the sourced script, it returns to the prompt and will
// never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang.
if (line.substr(0, 7) == "Error: ") {
logs.log_error("ABC: %s", line.c_str());
return false;
}
filt.next_line(line);
line.clear();
start = p + 1;

1
passes/techmap/lut2mux.cc
View file

@ -78,6 +78,7 @@ struct Lut2muxPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing LUT2MUX pass (convert $lut to $mux/$_MUX_).\n");
log("ARGS:"); for (auto &a: args) log(" [%s]", a.c_str()); log("\n");
size_t argidx;
bool word_mode = false;

31
passes/techmap/techmap.cc
View file

@ -338,9 +338,6 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c);
if (c->type.begins_with("\\$"))
c->type = c->type.substr(1);
if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
@ -445,13 +442,9 @@ struct TechmapWorker
if (handled_cells.count(cell) > 0)
continue;
std::string cell_type = cell->type.str();
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
if (celltypeMap.count(cell_type) == 0) {
if (assert_mode && cell_type.back() != '_')
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
if (celltypeMap.count(cell->type) == 0) {
if (assert_mode && !cell->type.ends_with("_"))
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
continue;
}
@ -463,7 +456,7 @@ struct TechmapWorker
if (GetSize(sig) == 0)
continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) {
for (auto &tpl_name : celltypeMap.at(cell->type)) {
RTLIL::Module *tpl = map->module(tpl_name);
RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input)
@ -490,12 +483,7 @@ struct TechmapWorker
log_assert(cell == module->cell(cell->name));
bool mapped_cell = false;
std::string cell_type = cell->type.str();
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
for (auto &tpl_name : celltypeMap.at(cell_type))
for (auto &tpl_name : celltypeMap.at(cell->type))
{
IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->module(tpl_name);
@ -517,8 +505,6 @@ struct TechmapWorker
if (!extmapper_name.empty())
{
cell->type = cell_type;
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type));
@ -945,11 +931,6 @@ struct TechmapWorker
RTLIL::Module *m = design->addModule(m_name);
tpl->cloneInto(m);
for (auto cell : m->cells()) {
if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
}
module_queue.insert(m);
}
@ -1178,7 +1159,7 @@ struct TechmapPass : public Pass {
std::vector<std::string> map_files;
std::vector<RTLIL::IdString> dont_map;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
int max_iter = -1;
size_t argidx;