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only check reg cells
This commit is contained in:
Stan Lee
parent
269b70c0f9
commit
f14eb4a7bb
1 changed files with 69 additions and 65 deletions
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@ -90,83 +90,87 @@ struct RegRenamePass : public Pass {
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pool<Wire *> wiresToRemove; // pool of wires to remove from the netlist
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for (auto cell : module->selected_cells()) {
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// Rename register output wires to corresponding testbench names
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std::smatch match;
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std::string name = cell->name.c_str();
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if (std::regex_match(name, match, reg_regex)) {
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// Only check register cell
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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// baseName is the part before _reg
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std::string baseName = match[1].str();
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// Rename register output wires to corresponding testbench names
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std::smatch match;
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std::string name = cell->name.c_str();
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if (std::regex_match(name, match, reg_regex)) {
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// Check if the register is a multi-bit register (look for [NUMBER] match in regex)
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bool isMultiBit = match.size() > 2 && match[2].matched;
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std::string indexStr;
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for (auto conn : cell->connections()) {
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *oldWire = conn.second.as_wire();
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// baseName is the part before _reg
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std::string baseName = match[1].str();
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// Skip if this wire is a module port (input/output)
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if (oldWire->port_input || oldWire->port_output) {
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log("Skipping port wire %s in register renaming for cell %s in module %s\n",
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oldWire->name.c_str(), log_id(cell), log_id(module));
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continue;
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}
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// Check if the register is a multi-bit register (look for [NUMBER] match in regex)
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bool isMultiBit = match.size() > 2 && match[2].matched;
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std::string indexStr;
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for (auto conn : cell->connections()) {
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *oldWire = conn.second.as_wire();
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// Different cases for multi-bit and single-bit registers
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if (isMultiBit) {
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// Index of the register
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int index = 0;
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try {
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index = std::stoi(match[2].str());
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} catch (const std::exception &e) {
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log_warning("Failed to convert index %s to integer in register %s: %s\n",
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match[2].str().c_str(), log_id(cell), e.what());
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// Skip if this wire is a module port (input/output)
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if (oldWire->port_input || oldWire->port_output) {
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log("Skipping port wire %s in register renaming for cell %s in module %s\n",
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oldWire->name.c_str(), log_id(cell), log_id(module));
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continue;
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}
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// Get or create the multi-bit wire
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Wire *newWire = module->wire(RTLIL::escape_id(baseName));
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if (newWire == nullptr) {
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// Wire doesn't exist, create it with the original register width
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int origRegWidth = vcd_reg_widths[baseName];
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if (origRegWidth == 0) {
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log_warning("Register '%s' not found in VCD file or has width 0\n", baseName.c_str());
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// Different cases for multi-bit and single-bit registers
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if (isMultiBit) {
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// Index of the register
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int index = 0;
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try {
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index = std::stoi(match[2].str());
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} catch (const std::exception &e) {
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log_warning("Failed to convert index %s to integer in register %s: %s\n",
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match[2].str().c_str(), log_id(cell), e.what());
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continue;
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}
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log("Creating multi-bit wire %s with width %d in module %s\n",
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baseName.c_str(), origRegWidth, log_id(module));
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newWire = module->addWire(RTLIL::escape_id(baseName), origRegWidth);
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}
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// Log that the new wire is being connected to the register
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log("Connecting register wire %s[%d] to bit %d of %s in module %s\n",
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newWire->name.c_str(), index, index, log_id(cell), log_id(module));
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// Get or create the multi-bit wire
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Wire *newWire = module->wire(RTLIL::escape_id(baseName));
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if (newWire == nullptr) {
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// Wire doesn't exist, create it with the original register width
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int origRegWidth = vcd_reg_widths[baseName];
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if (origRegWidth == 0) {
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log_warning("Register '%s' not found in VCD file or has width 0\n", baseName.c_str());
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continue;
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}
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log("Creating multi-bit wire %s with width %d in module %s\n",
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baseName.c_str(), origRegWidth, log_id(module));
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newWire = module->addWire(RTLIL::escape_id(baseName), origRegWidth);
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}
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// Replace all uses of oldWire with newWire[index]
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auto rewriter = [&](SigSpec &sig) {
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sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1));
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};
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module->rewrite_sigspecs(rewriter);
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// Log that the new wire is being connected to the register
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log("Connecting register wire %s[%d] to bit %d of %s in module %s\n",
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newWire->name.c_str(), index, index, log_id(cell), log_id(module));
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// Mark old wire for deletion
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log("Marking old wire %s for deletion in module %s\n",
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oldWire->name.c_str(), log_id(module));
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wiresToRemove.insert(oldWire);
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count++;
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} else {
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IdString target_name = RTLIL::escape_id(baseName);
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if (oldWire->name != target_name) {
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// Check if target name already exists
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if (module->wire(target_name)) {
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log("Skipping rename: wire %s already exists in module %s\n",
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target_name.c_str(), log_id(module));
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} else {
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// Rename single-bit register to correct name from RTL
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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oldWire->name.c_str(), target_name.c_str(), log_id(cell), log_id(module));
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module->rename(oldWire, target_name);
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count++;
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// Replace all uses of oldWire with newWire[index]
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auto rewriter = [&](SigSpec &sig) {
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sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1));
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};
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module->rewrite_sigspecs(rewriter);
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// Mark old wire for deletion
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log("Marking old wire %s for deletion in module %s\n",
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oldWire->name.c_str(), log_id(module));
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wiresToRemove.insert(oldWire);
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count++;
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} else {
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IdString target_name = RTLIL::escape_id(baseName);
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if (oldWire->name != target_name) {
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// Check if target name already exists
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if (module->wire(target_name)) {
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log("Skipping rename: wire %s already exists in module %s\n",
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target_name.c_str(), log_id(module));
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} else {
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// Rename single-bit register to correct name from RTL
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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oldWire->name.c_str(), target_name.c_str(), log_id(cell), log_id(module));
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module->rename(oldWire, target_name);
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count++;
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}
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}
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}
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}
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