mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 09:24:37 +00:00
Code Activity
11766 commits 122 branches 59 tags 72 MiB
Commit graph

1648 commits

Author SHA1 Message Date
Zachary Snow
58da181af9 Clearer for loop error messages 2020-07-25 10:37:16 -06:00
Zachary Snow
f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow
59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Zachary Snow
f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Claire Wolf
51ee0b683f Treat all bison warnings as errors in verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:57:31 +02:00
Claire Wolf
7a79843cc3 Use %precedence in verilog_parser.y 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:54:28 +02:00
Claire Wolf
24540291c7 Fix bison warnings for missing %empty 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:50:59 +02:00
Claire Wolf
1f4e452609 Run bison with -Wall for verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:49:36 +02:00
clairexen
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts 
Restore #2203 and #2244 and fix parser conflicts
 2020-07-15 11:49:09 +02:00
Kamil Rakoczy
02c071888b Add missing semicolons 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-15 10:15:13 +02:00
Claire Wolf
f9ed09423e Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-10 18:41:13 +02:00
Kamil Rakoczy
d77b3305d8 Fix S/R conflicts 
This commit fixes S/R conflicts introduced by commit 6f9be93.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:53 +02:00
Kamil Rakoczy
0ffaddee5e Fix R/R conflicts 
This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:01 +02:00
Kamil Rakoczy
de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
whitequark
dc35ef05f9 verilog_parser: turn S/R and R/R conflicts into hard errors. 
Fixes #2253.
 2020-07-09 19:36:59 +00:00
whitequark
9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
Lukasz Dalek
7e83a51fc9 Support logic typed parameters 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-07-06 09:18:48 +02:00
clairexen
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial 
verific: rewrite initial assume/asserts prior to elaboration
 2020-07-02 17:50:22 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master 
Allow constant function calls in for loops and generate if and case
 2020-06-30 17:38:49 +02:00
Miodrag Milanovic
561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Zachary Snow
27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Miodrag Milanovic
b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
Lukasz Dalek
6f9be939bd Parse macro call attached semicolon as empty expression 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0 Fix integer signing grammar 
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:35:56 +02:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators 
Add logic-assignments operators
 2020-06-26 07:30:27 +00:00
whitequark
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels 
Add support for optional labels
 2020-06-26 07:29:24 +00:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
Kamil Rakoczy
539087f417 Support missing sub-assign and and-assign operators 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 13:29:06 +02:00
Miodrag Milanovic
4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Lukasz Dalek
a4b4c22c96 Support missing xor-assign operator 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 14:32:12 +02:00
Lukasz Dalek
a8750b496e Support optional labels at the end of package definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Lukasz Dalek
3b81a1b809 Support optional labels at the end of module definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Kamil Rakoczy
22408f24c7 Add plus-assignment operator 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:54:30 +02:00
Kamil Rakoczy
416a66aee8 Add or-assignment operator 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:53:50 +02:00
Miodrag Milanovic
f993d18755 verific - import attributes for net buses as well 2020-06-24 11:01:06 +02:00
Kazuki Sakamoto
429d37ff41 static cast: simplify 2020-06-19 19:09:43 -07:00
Kazuki Sakamoto
185bbbe681 static cast: support changing size and signedness 
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
 2020-06-19 17:39:20 -07:00
whitequark
118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Anonymous Maarten
504f220619 MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
Anonymous Maarten
35008e6d40 MSVC cannot omit operand in conditional 2020-06-17 15:10:08 +02:00
clairexen
b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs 
Do not optimize away FFs in "prep" and Verific front-end
 2020-06-10 12:44:23 +02:00
Miodrag Milanovic
d6bec3ba1c verific - detect missing memory to prevent crash. 2020-06-10 11:27:44 +02:00
clairexen
5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040 
Add latch detection for use_case_method in part-select write
 2020-06-09 18:27:59 +02:00
Claire Wolf
3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Peter Crozier
f80b09fc58 Support 2D packed bit arrays in struct/union. 2020-06-09 13:52:09 +01:00
Peter Crozier
01ec681373 Support 2D bit arrays in structures. Optimise array indexing. 2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00