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Allow constant function calls in for loops and generate if and case

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This commit is contained in:
Zachary Snow 2020-06-26 19:52:36 -07:00
parent 4160acc0b1
commit 27cec16cda
3 changed files with 81 additions and 1 deletions
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6
frontends/ast/simplify.cc
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@ -1126,6 +1126,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
bool in_param_here = in_param;
if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
const_fold_here = true, in_param_here = true;
if (i == 0 && (type == AST_GENIF || type == AST_GENCASE))
in_param_here = true;
if (i == 1 && (type == AST_FOR || type == AST_GENFOR))
in_param_here = true;
if (type == AST_PARAMETER || type == AST_LOCALPARAM)
const_fold_here = true;
if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE))
@ -1942,7 +1946,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
continue;
buf = child->clone();
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, true)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");