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MSVC cannot omit operand in conditional

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Anonymous Maarten 2020-06-17 13:51:02 +02:00
parent c9c13c29df
commit 35008e6d40
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/verilog_parser.y
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@ -1481,7 +1481,7 @@ enum_name_decl:
delete $1;
SET_AST_NODE_LOC(node, @1, @1);
delete node->children[0];
node->children[0] = $2 ?: new AstNode(AST_NONE);
node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
astbuf2->children.push_back(node);
}
;