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Support optional labels at the end of module definition

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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
This commit is contained in:
Lukasz Dalek 2020-05-19 16:58:48 +02:00 • committed by Kamil Rakoczy
parent 0835a86e30
commit 3b81a1b809
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/verilog_parser.y
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@ -435,7 +435,7 @@ module:
mod->str = *$4;
append_attr(mod, $1);
delete $4;
} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
if (port_stubs.size() != 0)
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());