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Merge pull request #2168 from whitequark/assert-unused-exprs

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Use (and ignore) the expression provided to log_assert in NDEBUG builds
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clairexen 2020-06-25 18:21:51 +02:00 • committed by GitHub
commit c7d71f436d
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13 changed files with 46 additions and 43 deletions
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20
frontends/aiger/aigerparse.cc
View file

@ -69,7 +69,7 @@ struct ConstEvalAig
continue;
for (auto &it2 : it.second->connections())
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}
}
@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
for (int c = f.get(); c != EOF; c = f.get()) {
// XAIGER extensions
if (c == 'm') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
uint32_t lutNum = parse_xaiger_literal(f);
uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t lutSize = parse_xaiger_literal(f);
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
ConstEvalAig ce(module);
for (unsigned i = 0; i < lutNum; ++i) {
@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
int gray = j ^ (j >> 1);
ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
RTLIL::SigBit o(output_sig);
bool success YS_ATTRIBUTE(unused) = ce.eval(o);
bool success = ce.eval(o);
log_assert(success);
log_assert(o.wire == nullptr);
lut_mask[gray] = o.data;
@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
}
}
else if (c == 'r') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_debug("flopNum = %u\n", flopNum);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
@ -455,7 +455,7 @@ void AigerReader::parse_xaiger()
mergeability.emplace_back(parse_xaiger_literal(f));
}
else if (c == 's') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
initial_state.reserve(flopNum);
@ -469,15 +469,15 @@ void AigerReader::parse_xaiger()
}
else if (c == 'h') {
f.ignore(sizeof(uint32_t));
uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t version = parse_xaiger_literal(f);
log_assert(version == 1);
uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t ciNum = parse_xaiger_literal(f);
log_debug("ciNum = %u\n", ciNum);
uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t coNum = parse_xaiger_literal(f);
log_debug("coNum = %u\n", coNum);
piNum = parse_xaiger_literal(f);
log_debug("piNum = %u\n", piNum);
uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t poNum = parse_xaiger_literal(f);
log_debug("poNum = %u\n", poNum);
uint32_t boxNum = parse_xaiger_literal(f);
log_debug("boxNum = %u\n", boxNum);

2
frontends/ast/simplify.cc
View file

@ -778,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
did_something = true;
if (node->type == AST_ENUM) {
for (auto enode YS_ATTRIBUTE(unused) : node->children){
for (auto enode : node->children){
log_assert(enode->type==AST_ENUM_ITEM);
while (node->simplify(true, false, false, 1, -1, false, in_param))
did_something = true;

2
frontends/verific/verific.cc
View file

@ -1886,7 +1886,7 @@ struct VerificExtNets
new_net = new Net(name.c_str());
nl->Add(new_net);
Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
log_assert(n == ca_net);
}