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Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().

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This commit is contained in:
whitequark 2020-06-19 01:32:48 +00:00
parent 21692c4a2e
commit 118e4caa37
9 changed files with 26 additions and 26 deletions

20
frontends/aiger/aigerparse.cc
View file

@ -69,7 +69,7 @@ struct ConstEvalAig
continue;
for (auto &it2 : it.second->connections())
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}
}
@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
for (int c = f.get(); c != EOF; c = f.get()) {
// XAIGER extensions
if (c == 'm') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
uint32_t lutNum = parse_xaiger_literal(f);
uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t lutSize = parse_xaiger_literal(f);
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
ConstEvalAig ce(module);
for (unsigned i = 0; i < lutNum; ++i) {
@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
int gray = j ^ (j >> 1);
ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
RTLIL::SigBit o(output_sig);
bool success YS_ATTRIBUTE(unused) = ce.eval(o);
bool success = ce.eval(o);
log_assert(success);
log_assert(o.wire == nullptr);
lut_mask[gray] = o.data;
@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
}
}
else if (c == 'r') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_debug("flopNum = %u\n", flopNum);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
@ -455,7 +455,7 @@ void AigerReader::parse_xaiger()
mergeability.emplace_back(parse_xaiger_literal(f));
}
else if (c == 's') {
uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
initial_state.reserve(flopNum);
@ -469,15 +469,15 @@ void AigerReader::parse_xaiger()
}
else if (c == 'h') {
f.ignore(sizeof(uint32_t));
uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t version = parse_xaiger_literal(f);
log_assert(version == 1);
uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t ciNum = parse_xaiger_literal(f);
log_debug("ciNum = %u\n", ciNum);
uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t coNum = parse_xaiger_literal(f);
log_debug("coNum = %u\n", coNum);
piNum = parse_xaiger_literal(f);
log_debug("piNum = %u\n", piNum);
uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
uint32_t poNum = parse_xaiger_literal(f);
log_debug("poNum = %u\n", poNum);
uint32_t boxNum = parse_xaiger_literal(f);
log_debug("boxNum = %u\n", boxNum);

2
frontends/ast/simplify.cc
View file

@ -778,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
did_something = true;
if (node->type == AST_ENUM) {
for (auto enode YS_ATTRIBUTE(unused) : node->children){
for (auto enode : node->children){
log_assert(enode->type==AST_ENUM_ITEM);
while (node->simplify(true, false, false, 1, -1, false, in_param))
did_something = true;

2
frontends/verific/verific.cc
View file

@ -1882,7 +1882,7 @@ struct VerificExtNets
new_net = new Net(name.c_str());
nl->Add(new_net);
Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
log_assert(n == ca_net);
}

2
kernel/log.h
View file

@ -370,7 +370,7 @@ static inline void log_dump_val_worker(char *v) { log("%s", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }
static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
void log_dump_val_worker(RTLIL::IdString v);
void log_dump_val_worker(RTLIL::SigSpec v);
void log_dump_val_worker(RTLIL::State v);

6
kernel/modtools.h
View file

@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
port_add(cell, port, sig);
}
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) override
void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override
{
log_assert(module == mod);
@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
}
}
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) override
void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override
{
log_assert(module == mod);
auto_reload_module = true;
}
void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) override
void notify_blackout(RTLIL::Module *mod) override
{
log_assert(module == mod);
auto_reload_module = true;

2
passes/opt/opt_expr.cc
View file

@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
}
void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
const std::string &info, IdString out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);

4
passes/techmap/abc9_ops.cc
View file

@ -741,7 +741,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (ys_debug(1))
toposort.analyze_loops = true;
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
bool no_loops = toposort.sort();
if (ys_debug(1)) {
unsigned i = 0;
@ -1453,7 +1453,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
bool no_loops = toposort.sort();
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {

10
passes/techmap/dfflibmap.cc
View file

@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
char from_clk_pol = from[8];
char from_set_pol = from[9];
char from_clr_pol = from[10];
char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
char to_clk_pol = to[6];
char to_rst_pol = to[7];
char to_rst_val = to[8];
log_assert(from_clk_pol == to_clk_pol);
@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
char from_clk_pol = from[6];
char from_rst_pol = from[7];
char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
char to_clk_pol = to[6];
log_assert(from_clk_pol == to_clk_pol);

4
passes/tests/test_abcloop.cc
View file

@ -132,7 +132,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
bool ok = satgen.importCell(c);
log_assert(ok);
}
@ -182,7 +182,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
bool ok = satgen.importCell(c);
log_assert(ok);
}