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verilog_parser: turn S/R and R/R conflicts into hard errors.

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Fixes #2253.
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whitequark 2020-07-09 19:36:39 +00:00
parent 9c120b89ac
commit dc35ef05f9
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/Makefile.inc
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@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
$(Q) mkdir -p $(dir $@)
$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
$(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $<
frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc