1642 commits

Author	SHA1	Message	Date
Clifford Wolf	662a047815	Enable readline and tcl in mxe builds	2017-05-17 20:46:22 +02:00
Clifford Wolf	6934b862d3	Add missing AndnotGate() and OrnotGate() declarations to rtlil.h	2017-05-17 19:10:57 +02:00
Clifford Wolf	05cdd58c8d	Add $_ANDNOT_ and $_ORNOT_ gates	2017-05-17 09:08:29 +02:00
Clifford Wolf	fcb274a564	Add ConstEval defaultval feature	2017-04-05 11:25:22 +02:00
Clifford Wolf	b8d7f57f61	Add front-end detection for *.tcl files	2017-03-28 12:13:58 +02:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	c6d8d70109	Fix mingw compile issue (2nd attempt)	2017-02-23 14:21:02 +01:00
Clifford Wolf	0822b21844	Fix mingw compile issue (maybe.. I can't test it)	2017-02-23 13:59:02 +01:00
Clifford Wolf	e6d56d23b5	Fix eval implementation of $_NOR_	2017-02-16 12:17:03 +01:00
Clifford Wolf	828303791b	Add "yosys -w" for suppressing warnings	2017-02-12 11:11:00 +01:00
Clifford Wolf	63dfdb5d7f	Add log_wire() API	2017-02-11 11:08:36 +01:00
Clifford Wolf	aab58045a8	Fix undef propagation bug in $pmux SAT model	2017-02-05 22:43:33 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	b54972c112	Fix RTLIL::Memory::start_offset initialization	2017-01-25 17:00:59 +01:00
Clifford Wolf	6b2c23c721	Bugfix in RTLIL::SigSpec::remove2()	2016-12-31 16:14:42 +01:00
Clifford Wolf	33a22f8768	Simplified log_spacer() code	2016-12-23 02:06:46 +01:00
Clifford Wolf	a0dff87a57	Added "yosys -W regex"	2016-12-22 23:41:44 +01:00
Clifford Wolf	f144adec58	Added AIGER back-end to automatic back-end detection	2016-12-21 10:16:47 +01:00
Clifford Wolf	00761de1b7	Bugfix in comment handling	2016-12-13 13:48:09 +01:00
Clifford Wolf	a926a6afc2	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
Clifford Wolf	fa535c0b00	Some minor build fixes for Visual C	2016-10-14 18:36:02 +02:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	59508c99b4	define PATH_MAX if not defined by limits.h	2016-10-11 12:12:09 +02:00
Clifford Wolf	cb7dbf4070	Improvements in assertpmux	2016-09-07 12:42:16 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	23afeadb5e	Fixed handling of transparent bram rd ports on ROMs	2016-08-27 17:06:22 +02:00
Clifford Wolf	f8a77abfac	Added glob support to all front-ends	2016-08-22 15:05:57 +02:00
William D. Jones	5299b17056	Add MSYS2-compatible build.	2016-08-16 14:41:59 -04:00
Clifford Wolf	5767e4bc4d	Use _Exit(0) on win32, always use _Exit(1) in log_error()	2016-08-16 09:38:54 +02:00
Clifford Wolf	39da8eddae	Added log_const() API	2016-08-09 19:56:10 +02:00
Yury Gribov	f7730d43bb	Use /proc/self/exe on Cygwin as well.	2016-08-08 12:00:27 +02:00
Clifford Wolf	8d88fcb270	Added SatGen support for $anyconst	2016-07-27 15:52:20 +02:00
Clifford Wolf	9540be1d45	Removed $predict support from SatGen	2016-07-27 15:44:11 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	a7b0769623	Added "read_verilog -dump_rtlil"	2016-07-27 15:40:17 +02:00
Clifford Wolf	8537c4d206	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	2016-07-25 16:39:25 +02:00
Clifford Wolf	b1c432af56	Improvements in CellEdgesDatabase	2016-07-24 17:21:53 +02:00
Clifford Wolf	f162b858f2	Added CellEdgesDatabase API	2016-07-24 13:59:57 +02:00
Clifford Wolf	89deb412c6	Added satgen initstate support	2016-07-22 10:28:45 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Ruben Undheim	a8200a773f	A few modifications after pull request comments ... - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h	2016-06-18 14:23:38 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	ebece2b8d5	Added $sop SAT model	2016-06-17 17:47:30 +02:00
Clifford Wolf	95757efb25	Improved support for $sop cells	2016-06-17 16:31:16 +02:00
Clifford Wolf	52bb1b968d	Added $sop cell type and "abc -sop"	2016-06-17 13:50:09 +02:00