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https://github.com/YosysHQ/yosys
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Added $initstate cell type and vlog function
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parent
d7763634b6
commit
5c166e76e5
7 changed files with 54 additions and 4 deletions
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@ -117,6 +117,7 @@ struct CellTypes
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setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
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setup_type("$equiv", {A, B}, {Y}, true);
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}
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@ -1024,6 +1024,12 @@ namespace {
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return;
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}
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if (cell->type == "$initstate") {
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port("\\Y", 1);
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check_expected();
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return;
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}
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if (cell->type == "$equiv") {
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port("\\A", 1);
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port("\\B", 1);
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@ -69,7 +69,7 @@ struct SatGen
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SigPool initial_state;
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std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
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std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;
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std::map<std::string, RTLIL::SigSpec> expects_a, expects_en;
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std::map<std::string, RTLIL::SigSpec> predict_a, predict_en;
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std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;
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bool ignore_div_by_zero;
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bool model_undef;
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@ -1350,8 +1350,8 @@ struct SatGen
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if (cell->type == "$predict")
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{
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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expects_a[pf].append((*sigmap)(cell->getPort("\\A")));
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expects_en[pf].append((*sigmap)(cell->getPort("\\EN")));
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predict_a[pf].append((*sigmap)(cell->getPort("\\A")));
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predict_en[pf].append((*sigmap)(cell->getPort("\\EN")));
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return true;
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}
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