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A few modifications after pull request comments

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- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
This commit is contained in:
Ruben Undheim 2016-06-18 14:13:36 +02:00
parent 178ff3e7f6
commit a8200a773f
3 changed files with 4 additions and 5 deletions
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2
kernel/rtlil.cc
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@ -304,7 +304,7 @@ RTLIL::Design::~Design()
{
for (auto it = modules_.begin(); it != modules_.end(); ++it)
delete it->second;
for (auto n : packages)
for (auto n : verilog_packages)
delete n;
}

3
kernel/rtlil.h
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@ -18,7 +18,6 @@
*/
#include "kernel/yosys.h"
#include "frontends/ast/ast.h"
#ifndef RTLIL_H
#define RTLIL_H
@ -793,7 +792,7 @@ struct RTLIL::Design
int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<AST::AstNode*> packages;
std::vector<AST::AstNode*> verilog_packages;
std::vector<RTLIL::Selection> selection_stack;
dict<RTLIL::IdString, RTLIL::Selection> selection_vars;