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Added $anyseq cell type

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This commit is contained in:
Clifford Wolf 2016-10-14 15:24:03 +02:00
parent 2733994aeb
commit bdc316db50
11 changed files with 40 additions and 11 deletions
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1
kernel/celltypes.h
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@ -118,6 +118,7 @@ struct CellTypes
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$equiv", {A, B}, {Y}, true);
}

11
kernel/rtlil.cc
View file

@ -1037,7 +1037,7 @@ namespace {
return;
}
if (cell->type == "$anyconst") {
if (cell->type.in("$anyconst", "$anyseq")) {
port("\\Y", param("\\WIDTH"));
check_expected();
return;
@ -2009,6 +2009,15 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
return sig;
}
RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, "$anyseq");
cell->setParam("\\WIDTH", width);
cell->setPort("\\Y", sig);
return sig;
}
RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
{
RTLIL::SigSpec sig = addWire(NEW_ID);

1
kernel/rtlil.h
View file

@ -1108,6 +1108,7 @@ public:
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d);
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1);
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1);
RTLIL::SigSpec Initstate (RTLIL::IdString name);
};

9
kernel/satgen.h
View file

@ -1332,8 +1332,8 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\Y"), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Y"), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
@ -1341,6 +1341,11 @@ struct SatGen
return true;
}
if (cell->type == "$anyseq")
{
return true;
}
if (cell->type == "$_BUF_" || cell->type == "$equiv")
{
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);