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Added CellEdgesDatabase API

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This commit is contained in:
Clifford Wolf 2016-07-24 13:59:57 +02:00
parent 54966679df
commit f162b858f2
4 changed files with 250 additions and 1 deletions
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88
kernel/celledges.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/celledges.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
void add_bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
IdString A = "\\A", Y = "\\Y";
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int a_width = GetSize(cell->getPort(A));
int y_width = GetSize(cell->getPort(Y));
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
db->add_edge(cell, A, i, Y, i);
else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i);
}
}
void add_bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
IdString A = "\\A", B = "\\B", Y = "\\Y";
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int a_width = GetSize(cell->getPort(A));
int b_width = GetSize(cell->getPort(B));
int y_width = GetSize(cell->getPort(Y));
if (cell->type == "$and" && !is_signed) {
if (a_width > b_width)
a_width = b_width;
else
b_width = a_width;
}
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
db->add_edge(cell, A, i, Y, i);
else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i);
if (i < b_width)
db->add_edge(cell, B, i, Y, i);
else if (is_signed && b_width > 0)
db->add_edge(cell, B, b_width-1, Y, i);
}
}
PRIVATE_NAMESPACE_END
bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
{
if (cell->type.in("$not", "$pos")) {
add_bitwise_unary_op(this, cell);
return true;
}
if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
add_bitwise_binary_op(this, cell);
return true;
}
return false;
}

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kernel/celledges.h Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef CELLEDGES_H
#define CELLEDGES_H
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
YOSYS_NAMESPACE_BEGIN
struct AbstractCellEdgesDatabase
{
virtual ~AbstractCellEdgesDatabase() { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) = 0;
bool add_cell(RTLIL::Cell *cell);
};
struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
{
SigMap &sigmap;
dict<SigBit, pool<SigBit>> db;
FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[from_sigbit].insert(to_sigbit);
}
};
struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
{
SigMap &sigmap;
dict<SigBit, pool<SigBit>> db;
RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[to_sigbit].insert(from_sigbit);
}
};
YOSYS_NAMESPACE_END
#endif