SergeyDegtyar
d945b8a357
Fix all comments from PR
2019-08-21 21:52:07 +03:00
SergeyDegtyar
b835ec37cb
Add temp directory
2019-08-21 07:53:34 +03:00
Eddie Hung
fce8dc7db2
Add test
2019-08-20 20:05:16 -07:00
SergeyDegtyar
71dd412ac5
Fix tests; Remove simulation;
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- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
2019-08-20 15:52:25 +03:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen
2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12
Add test case for real parameters
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-20 11:38:21 +02:00
SergeyDegtyar
153ec0541c
Add new tests for ice40 architecture
2019-08-20 07:50:05 +03:00
whitequark
4a942ba7b9
proc_clean: fix order of switch insertion.
...
Fixes #1268 .
2019-08-19 16:44:23 +00:00
Clifford Wolf
21699e5840
Add *.sv to tests/simple_abc9/.gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-19 13:04:57 +02:00
Clifford Wolf
1e3dd0a2da
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
2019-08-19 13:04:06 +02:00
Eddie Hung
e34f2de55d
Merge remote-tracking branch 'origin/master' into clifford/testfast
2019-08-18 21:29:15 -07:00
Eddie Hung
f5170a7eda
Removal of more stat calls from tests
2019-08-18 21:28:45 -07:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
9e940f1276
Speed up "make test" and related cleanups
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:37:07 +02:00
Clifford Wolf
f20be90436
Add test for pmtest_test "reduce" demo pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:05:10 +02:00
Eddie Hung
51d28645da
Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
2019-08-16 13:40:29 -07:00
Clifford Wolf
40c40d9f5d
Do not use Verific in tests/various/write_gzip.ys
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:22:46 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310f54bf1631f
2019-08-12 12:06:45 -07:00
Eddie Hung
88d5185596
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
2019-08-11 21:13:40 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Eddie Hung
0adf81cb91
Add $alu tests
2019-08-09 12:13:17 -07:00
Eddie Hung
8350dfb809
Add alumacc versions of opt_expr tests
2019-08-09 10:30:53 -07:00
Eddie Hung
9300111601
Add new $alu test, remove wreduce
2019-08-09 10:22:06 -07:00
Eddie Hung
313c9ec8df
Cleanup some more
2019-08-09 10:13:49 -07:00
Eddie Hung
d9c1664462
Simplify opt_expr tests using equiv_opt
2019-08-09 10:08:17 -07:00
Eddie Hung
8bf45f34c4
Remove dump call
2019-08-07 21:36:02 -07:00
Eddie Hung
2b6cdfb39f
Move tests/various/opt* into tests/opt/
2019-08-07 21:35:48 -07:00
Eddie Hung
d5e8c0e6d3
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
2019-08-07 21:33:56 -07:00
Eddie Hung
35bf509603
Add testcase from removed opt_ff.{v,ys}
2019-08-07 21:31:32 -07:00
Eddie Hung
4545bf482f
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
2019-08-07 16:48:38 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic
067b44938c
Fix wrong results when opt_share called before opt_clean
2019-08-07 09:30:58 +02:00
Eddie Hung
2d1b517b01
Add signed opt_expr tests
2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22
Add signed test
2019-08-06 15:38:43 -07:00
Eddie Hung
51b39219cd
Move LSB tests from wreduce to opt_expr
2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
David Shah
3a3da678ad
Add test for writing gzip-compressed files
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
Bogdan Vukobratovic
6a796accc0
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic
d8be5ce6ba
Tabs to spaces in opt_share examples
2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic
280c4e7794
Fix spacing in opt_share tests, change wording in opt_share help
2019-08-03 12:28:46 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
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Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
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This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
David Shah
933db0410e
Add support for reading gzip'd input files
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Eddie Hung
c926eeb43a
Add another test
2019-07-19 14:02:46 -07:00
Eddie Hung
5bd088a686
Add one more test with trimming Y_WIDTH of $sub
2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df
Be more explicit
2019-07-19 12:53:18 -07:00
Eddie Hung
4e9b1d36fa
Add tests for sub too
2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2
Add test
2019-07-19 12:43:02 -07:00
