Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen

tests/fsm/run-test.sh

@@ -6,7 +6,7 @@
 set -e
 
 OPTIND=1
-count=100
+count=50
 seed=""    # default to no seed specified
 while getopts "c:S:" opt
 do

tests/opt/opt_ff.v

@@ -1,21 +0,0 @@
-module top(
-    input clk,
-    input rst,
-    input [2:0] a,
-    output [1:0] b
-);
-    reg [2:0] b_reg;
-    initial begin
-        b_reg <= 3'b0;
-    end
-
-    assign b = b_reg[1:0];
-    always @(posedge clk or posedge rst) begin
-        if(rst) begin
-            b_reg <= 3'b0;
-        end else begin
-            b_reg <= a;
-        end
-    end
-endmodule
-

tests/opt/opt_ff.ys

@@ -1,3 +0,0 @@
-read_verilog opt_ff.v
-synth_ice40
-ice40_unlut

tests/opt/opt_lut.ys

@@ -1,4 +1,2 @@
 read_verilog opt_lut.v
-synth_ice40
-ice40_unlut
-equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40

tests/opt/opt_rmdff.ys

@@ -19,8 +19,8 @@ hierarchy -top equiv
 equiv_simple -undef
 equiv_status -assert
 
-design -load gold
-stat
-
-design -load gate
-stat
+#design -load gold
+#stat
+#
+#design -load gate
+#stat

tests/opt/opt_rmdff_sat.ys

@@ -1,4 +1,4 @@
-read_verilog opt_ff_sat.v
+read_verilog opt_rmdff_sat.v
 prep -flatten
 opt_rmdff -sat
 synth

tests/opt/opt_share_add_sub.v

@@ -0,0 +1,10 @@
+module opt_share_test(
+  input [15:0]  a,
+  input [15:0]  b,
+  input         sel,
+  output [15:0] res,
+  );
+
+  assign res = {sel ? a + b : a - b};
+
+endmodule

tests/opt/opt_share_add_sub.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_add_sub.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 1 -module merged t:$alu

tests/opt/opt_share_cat.v

@@ -0,0 +1,15 @@
+module opt_share_test(
+  input [15:0]  a,
+  input [15:0]  b,
+  input [15:0]  c,
+  input [15:0]  d,
+  input         sel,
+  output [63:0] res,
+  );
+
+  reg [31: 0]   cat1 = {a+b, c+d};
+  reg [31: 0]   cat2 = {a-b, c-d};
+
+  assign res = {b, sel ? cat1 : cat2, a};
+
+endmodule

tests/opt/opt_share_cat.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_cat.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 2 -module merged t:$alu

tests/opt/opt_share_cat_multiuser.v

@@ -0,0 +1,22 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input             sel,
+  output reg [47:0] res,
+  );
+
+  wire [15:0]       add_res = a+b;
+  wire [15:0]       sub_res = a-b;
+  wire [31: 0]      cat1 = {add_res, c+d};
+  wire [31: 0]      cat2 = {sub_res, c-d};
+
+  always @* begin
+    case(sel)
+      0: res = {cat1, add_res};
+      1: res = {cat2, add_res};
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_cat_multiuser.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_cat_multiuser.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 3 -module merged t:$alu

tests/opt/opt_share_diff_port_widths.v

@@ -0,0 +1,21 @@
+module opt_share_test(
+  input [15:0]       a,
+  input [15:0]       b,
+  input [15:0]       c,
+  input [1:0]      sel,
+  output reg [15:0] res
+  );
+
+  wire [15:0]       add0_res = a+b;
+  wire [15:0]       add1_res = a+c;
+
+  always @* begin
+    case(sel)
+      0: res = add0_res[10:0];
+      1: res = add1_res[10:0];
+      2: res = a - b;
+      default: res = 32'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_diff_port_widths.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_diff_port_widths.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 2 -module merged t:$alu

tests/opt/opt_share_extend.v

@@ -0,0 +1,18 @@
+module opt_share_test(
+  input signed [7:0]       a,
+  input signed [10:0]      b,
+  input signed [15:0]      c,
+  input [1:0]              sel,
+  output reg signed [15:0] res
+  );
+
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      default: res = 16'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_extend.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_extend.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 1 -module merged t:$alu

tests/opt/opt_share_large_pmux_cat.v

@@ -0,0 +1,21 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [2:0]       sel,
+  output reg [31:0] res
+  );
+
+  always @* begin
+    case(sel)
+      0: res = {a + b, a};
+      1: res = {a - b, b};
+      2: res = {a + c, c};
+      3: res = {a - c, a};
+      4: res = {b, b};
+      5: res = {c, c};
+      default: res = 32'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_large_pmux_cat.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_large_pmux_cat.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 1 -module merged t:$alu

tests/opt/opt_share_large_pmux_cat_multipart.v

@@ -0,0 +1,25 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input [2:0]       sel,
+  output reg [31:0] res
+  );
+
+  wire [15:0]       add0_res = a+d;
+
+  always @* begin
+    case(sel)
+      0: res = {add0_res, a};
+      1: res = {a - b, add0_res[7], 15'b0};
+      2: res = {b-a, b};
+      3: res = {d, b - c};
+      4: res = {d, b - a};
+      5: res = {c, d};
+      6: res = {a - c, b-d};
+      default: res = 32'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_large_pmux_cat_multipart.ys

@@ -0,0 +1,14 @@
+read_verilog opt_share_large_pmux_cat_multipart.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 4 -module merged t:$alu

tests/opt/opt_share_large_pmux_multipart.v

@@ -0,0 +1,23 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [15:0]      d,
+  input [2:0]       sel,
+  output reg [15:0] res
+  );
+
+  always @* begin
+    case(sel)
+      0: res = a + d;
+      1: res = a - b;
+      2: res = b;
+      3: res = b - c;
+      4: res = b - a;
+      5: res = c;
+      6: res = a - c;
+      default: res = 16'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_large_pmux_multipart.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_large_pmux_multipart.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 2 -module merged t:$alu

tests/opt/opt_share_large_pmux_part.v

@@ -0,0 +1,21 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [2:0]       sel,
+  output reg [15:0] res
+  );
+
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      3: res = a - c;
+      4: res = b;
+      5: res = c;
+      default: res = 16'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_large_pmux_part.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_large_pmux_part.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 1 -module merged t:$alu

tests/opt/opt_share_mux_tree.v

@@ -0,0 +1,18 @@
+module opt_share_test(
+  input [15:0]      a,
+  input [15:0]      b,
+  input [15:0]      c,
+  input [1:0]       sel,
+  output reg [15:0] res
+  );
+
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      default: res = 16'bx;
+    endcase
+  end
+
+endmodule

tests/opt/opt_share_mux_tree.ys

@@ -0,0 +1,13 @@
+read_verilog opt_share_mux_tree.v
+proc;;
+copy opt_share_test merged
+
+alumacc merged
+opt merged
+opt_share merged
+opt_clean merged
+
+miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
+sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
+
+select -assert-count 1 -module merged t:$alu

tests/opt_share/.gitignore

@@ -0,0 +1 @@
+temp

tests/opt_share/generate.py

@@ -0,0 +1,86 @@
+#!/usr/bin/env python3
+
+import argparse
+import sys
+import random
+from contextlib import contextmanager
+
+
+@contextmanager
+def redirect_stdout(new_target):
+    old_target, sys.stdout = sys.stdout, new_target
+    try:
+        yield new_target
+    finally:
+        sys.stdout = old_target
+
+
+def random_plus_x():
+    return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^'])
+
+
+def maybe_plus_x(expr):
+    if random.randint(0, 4) == 0:
+        return "(%s %s)" % (expr, random_plus_x())
+    else:
+        return expr
+
+
+parser = argparse.ArgumentParser(
+    formatter_class=argparse.ArgumentDefaultsHelpFormatter)
+parser.add_argument('-S', '--seed', type=int, help='seed for PRNG')
+parser.add_argument('-c',
+                    '--count',
+                    type=int,
+                    default=100,
+                    help='number of test cases to generate')
+args = parser.parse_args()
+
+if args.seed is not None:
+    print("PRNG seed: %d" % args.seed)
+    random.seed(args.seed)
+
+for idx in range(args.count):
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
+        with redirect_stdout(f):
+            print('module uut_%05d(a, b, c, s, y);' % (idx))
+            op = random.choice([
+                random.choice(['+', '-', '*', '/', '%']),
+                random.choice(['<', '<=', '==', '!=', '===', '!==', '>=',
+                               '>']),
+                random.choice(['<<', '>>', '<<<', '>>>']),
+                random.choice(['|', '&', '^', '~^', '||', '&&']),
+            ])
+            print('  input%s [%d:0] a;' % (random.choice(['', ' signed']), 8))
+            print('  input%s [%d:0] b;' % (random.choice(['', ' signed']), 8))
+            print('  input%s [%d:0] c;' % (random.choice(['', ' signed']), 8))
+            print('  input s;')
+            print('  output [%d:0] y;' % 8)
+            ops1 = ['a', 'b']
+            ops2 = ['a', 'c']
+            random.shuffle(ops1)
+            random.shuffle(ops2)
+            cast1 = random.choice(['', '$signed', '$unsigned'])
+            cast2 = random.choice(['', '$signed', '$unsigned'])
+            print('  assign y = (s ? %s(%s %s %s) : %s(%s %s %s));' %
+                  (cast1, ops1[0], op, ops1[1],
+                   cast2, ops2[0], op, ops2[1]))
+            print('endmodule')
+
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
+        with redirect_stdout(f):
+            print('read_verilog temp/uut_%05d.v' % idx)
+            print('proc;;')
+            print('copy uut_%05d gold' % idx)
+            print('rename uut_%05d gate' % idx)
+            print('tee -a temp/all_share_log.txt log')
+            print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx)
+            print('tee -a temp/all_share_log.txt opt gate')
+            print('tee -a temp/all_share_log.txt opt_share gate')
+            print('tee -a temp/all_share_log.txt opt_clean gate')
+            print(
+                'miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter'
+            )
+            print(
+                'sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter'
+            )

tests/opt_share/run-test.sh

@@ -0,0 +1,39 @@
+#!/bin/bash
+
+# run this test many times:
+# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
+
+set -e
+
+OPTIND=1
+count=100
+seed=""    # default to no seed specified
+while getopts "c:S:" opt
+do
+  case "$opt" in
+		c) count="$OPTARG" ;;
+		S) seed="-S $OPTARG" ;;
+  esac
+done
+shift "$((OPTIND-1))"
+
+rm -rf temp
+mkdir -p temp
+echo "generating tests.."
+python3 generate.py -c $count $seed
+
+echo "running tests.."
+for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
+	echo -n "[$i]"
+	idx=$( printf "%05d" $i )
+	../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys
+done
+echo
+
+failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [246] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) )
+if [ -n "$failed_share" ]; then
+	echo "Resource sharing failed for the following test cases: $failed_share"
+	false
+fi
+
+exit 0

tests/simple_abc9/run-test.sh

@@ -18,5 +18,6 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
+cp ../simple/*.sv .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"

tests/various/.gitignore

@@ -2,3 +2,4 @@
 /*.out
 /write_gzip.v
 /write_gzip.v.gz
+/run-test.mk

tests/various/muxpack.ys

@@ -6,7 +6,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -21,7 +21,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -52,7 +52,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -67,7 +67,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -82,7 +82,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -97,7 +97,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -112,7 +112,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -127,7 +127,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -142,7 +142,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 7 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -157,7 +157,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 4 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -172,7 +172,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 3 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -204,7 +204,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -222,7 +222,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -240,7 +240,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -258,7 +258,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate

tests/various/run-test.sh

@@ -1,12 +1,20 @@
 #!/usr/bin/env bash
 set -e
+{
+echo "all::"
 for x in *.ys; do
-	echo "Running $x.."
-	../../yosys -ql ${x%.ys}.log $x
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-		echo "Running $s.."
-		bash $s
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
 	fi
 done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk

tests/various/shregmap.ys

@@ -11,7 +11,7 @@ shregmap -init
 
 opt
 
-stat
+# stat
 # show -width
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__SHREG_DFF_P_
@@ -26,11 +26,11 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+#design -load gold
+#stat
 
-design -load gate
-stat
+#design -load gate
+#stat
 
 ##########
 
@@ -43,9 +43,9 @@ design -save gold
 simplemap t:$dff t:$dffe
 shregmap -tech xilinx
 
-stat
+#stat
 # show -width
-write_verilog -noexpr -norename
+# write_verilog -noexpr -norename
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__XILINX_SHREG_
 
@@ -59,8 +59,8 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+# design -load gold
+# stat
 
-design -load gate
-stat
+# design -load gate
+# stat

tests/various/wreduce.ys

@@ -36,7 +36,6 @@ design -save gold
 opt_expr
 wreduce
 
-dump
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
@@ -46,3 +45,35 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+##########
+
+# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
+design -reset
+read_verilog <<EOT
+module top(
+    input clk,
+    input rst,
+    input [2:0] a,
+    output [1:0] b
+);
+    reg [2:0] b_reg;
+    initial begin
+        b_reg <= 3'b0;
+    end
+
+    assign b = b_reg[1:0];
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+            b_reg <= 3'b0;
+        end else begin
+            b_reg <= a;
+        end
+    end
+endmodule
+EOT
+
+proc
+wreduce
+
+select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i

tests/various/write_gzip.ys

@@ -1,4 +1,4 @@
-read -vlog2k <<EOT
+read_verilog <<EOT
 module top(input a, output y);
 assign y = !a;
 endmodule
@@ -10,7 +10,7 @@ design -reset
 
 ! rm -f write_gzip.v
 ! gunzip write_gzip.v.gz
-read -vlog2k write_gzip.v
+read_verilog write_gzip.v
 ! rm -f write_gzip.v
 hierarchy -top top
 select -assert-any top