905 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	c3ffbf6fae	WIP	2026-06-12 00:18:53 +02:00
Emil J. Tywoniak	afdae7b87e	WIP	2026-06-11 20:02:02 +02:00
Emil J. Tywoniak	8e522b08c0	WIP	2026-06-11 13:17:54 +02:00
Emil J. Tywoniak	f592f2f3af	WIP	2026-06-10 19:22:53 +02:00
Emil J. Tywoniak	2117af318c	WIP	2026-06-10 14:54:48 +02:00
Emil J. Tywoniak	d13dfc21f4	WIP	2026-06-10 14:54:48 +02:00
Emil J. Tywoniak	1a8a95b472	rtlil: fix masquerade	2026-06-10 14:54:45 +02:00
Emil J. Tywoniak	2d3b7e9c92	rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge)	2026-06-10 14:54:43 +02:00
Emil J. Tywoniak	734593e12d	rtlil: Module::clone attaches to source design; callers use clone(dst)	2026-06-10 14:54:34 +02:00
Emil J. Tywoniak	8f8a07efee	rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer	2026-06-10 14:54:31 +02:00
Emil J. Tywoniak	f1edb571f2	rtlil: evacuate src_id_ from AttrObject to per-Design meta vector	2026-06-10 14:54:05 +02:00
Emil J. Tywoniak	3424c00cd0	twine	2026-06-10 14:53:45 +02:00
Emil J. Tywoniak	c3457e2e5c	WIP	2026-06-10 14:52:50 +02:00
Emil J. Tywoniak	cef8186c4a	patch: infer leaves for gc	2026-05-28 12:56:13 +02:00
Emil J. Tywoniak	1cd0d37511	patch: instead of cell->cell, use port->sig rewrites	2026-05-27 18:07:01 +02:00
Emil J. Tywoniak	9f22b9d2a0	patch: source transfer	2026-05-23 00:10:02 +02:00
Emil J. Tywoniak	db1c1d4359	patch: working multi-cell signorm invariant	2026-05-23 00:10:00 +02:00
Emil J. Tywoniak	8c26ecd2a6	patch: WIP multicell patch test	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	d2ae9b48e4	patch: signorm, move	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	b7ea32dbee	patch: unique heap	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	89e5c4ccca	test_patch total basics	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	dcc68e49fb	check: check bufnorm too	2026-05-22 18:41:50 +02:00
Emil J. Tywoniak	4bff2e6340	check: check signorm indices and wires	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	350385f5a2	check: fix memory bug in $connect	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	451e01d0a4	design: properly switch signorm mode when restoring saved designs	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	bd8738de15	connect: remove input ports on conflict	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	21bed1a411	design: fix signorm commit connectivity to design	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	faa1a1065c	flatten: redo signormalization to work around fanout issue	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4f665d6efc	signorm: disable passes that use rewrite_sigspecs	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	8267dee75a	check: stitch info about $connect ports together for driver analysis	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	5c5df513d1	abstract: skip $input_port cells	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	68bb5c6b94	signorm: disable in passes that use swap_names	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	dcc4cbea2f	check: don't fail on $input_port	2026-05-22 18:37:13 +02:00
Miodrag Milanovic	75dcbe03c6	Convert RTLIL::unescape_id of IdString to unescape()	2026-05-16 19:49:45 +02:00
Miodrag Milanovic	8bbc3c359c	Remove id2cstr uses in our code base	2026-05-16 19:49:45 +02:00
Miodrag Milanović	1d87cefd80	Merge pull request #5882 from YosysHQ/std_cpp20 ... Bump required standard to C++20	2026-05-15 13:13:43 +00:00
Miodrag Milanovic	4a7878b17f	Fixing couple more conversion errors	2026-05-14 15:58:58 +02:00
Miodrag Milanovic	c6f53aec5f	Fixed log_id instances used with fprintf	2026-05-14 11:28:16 +02:00
Miodrag Milanovic	90e019e319	Fix compiling on GCC11	2026-05-13 10:11:36 +02:00
Codexplorer	e41b969da2	Refactored uses of log_id()	2026-05-08 20:59:24 -07:00
N. Engelhardt	240f7030b2	xprop: ignore $scopeinfo cells	2026-04-21 10:52:50 +02:00
Emil J	9746bd3897	Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection ... setundef: respect selection for cells, processes, and connections	2026-03-18 22:53:06 +00:00
abhinavputhran	47c2257f82	setundef: more tests! and wire selection in -init mode	2026-03-08 19:41:31 -04:00
abhinavputhran	5048dac854	setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer	2026-03-06 18:12:03 -05:00
abhinavputhran	9e666c727f	setundef: respect selection in -undriven mode	2026-03-06 10:37:59 -05:00
Miodrag Milanovic	52533b0d1c	Update opt_lut_ins and stat for analogdevices and remove ecp5	2026-03-06 09:10:36 +01:00
abhinavputhran	6cd66aed47	setundef: rename process loop variable and respect selection in -init mode	2026-03-05 17:51:01 -05:00
abhinavputhran	df283fa1c9	setundef: use selected_processes() per review feedback	2026-03-05 11:22:00 -05:00
abhinavputhran	4e54853e35	setundef: use selected_processes() per review feedback	2026-03-05 11:16:07 -05:00
abhinavputhran	94c789e9c8	setundef: respect selection for cells, processes, and connections ... Previously, setundef would rewrite sigspecs in all cells, processes, and connections regardless of the active selection. Only modules and memories were correctly filtered by selection. Fix by using module->selected_cells() for cells, adding a module->selected() check for processes, and checking wire selection on the lhs of each connection before rewriting. Fixes #5624	2026-03-04 17:48:35 -05:00