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rtlil: Module::clone attaches to source design; callers use clone(dst)

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This commit is contained in:
Emil J. Tywoniak 2026-06-05 21:15:24 +02:00
parent 8f8a07efee
commit 734593e12d
4 changed files with 7 additions and 5 deletions
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2
kernel/rtlil.cc
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@ -3251,6 +3251,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
RTLIL::Module *RTLIL::Module::clone() const
{
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->design = design;
new_mod->name = name;
cloneInto(new_mod);
return new_mod;
@ -3259,6 +3260,7 @@ RTLIL::Module *RTLIL::Module::clone() const
RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, bool src_id_verbatim) const
{
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->design = dst;
new_mod->name = name;
dst->add(new_mod);
cloneInto(new_mod, src_id_verbatim);

6
passes/cmds/bugpoint.cc
View file

@ -183,7 +183,7 @@ struct BugpointPass : public Pass {
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto module : design->modules())
design_copy->add(module->clone());
module->clone(design_copy);
Pass::call(design_copy, "proc_clean -quiet");
Pass::call(design_copy, "clean -purge");
@ -196,7 +196,7 @@ struct BugpointPass : public Pass {
{
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto module : design->modules())
design_copy->add(module->clone());
module->clone(design_copy);
int index = 0;
if (modules)
@ -678,7 +678,7 @@ struct BugpointPass : public Pass {
Pass::call(design, "design -reset");
crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
for (auto module : crashing_design->modules())
design->add(module->clone());
module->clone(design);
delete crashing_design;
}

2
passes/techmap/extract.cc
View file

@ -596,7 +596,7 @@ struct ExtractPass : public Pass {
}
for (auto mod : saved_designs.at(filename.substr(1))->modules())
if (!map->has(mod->name))
map->add(mod->clone());
mod->clone(map);
}
else
{

2
passes/techmap/techmap.cc
View file

@ -1225,7 +1225,7 @@ struct TechmapPass : public Pass {
}
for (auto mod : saved_designs.at(fn.substr(1))->modules())
if (!map->module(mod->name))
map->add(mod->clone());
mod->clone(map);
} else {
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
}