1472 commits

Author	SHA1	Message	Date
Clifford Wolf	95944eb69e	make all vector-size related integer params in $mem sim model signed ... this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.	2015-04-05 17:26:53 +02:00
Clifford Wolf	706631225e	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	2015-04-05 09:45:14 +02:00
Clifford Wolf	c52a4cdeed	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00
Clifford Wolf	e468d4cc60	Fixes in cmos_cells.v	2015-03-25 09:00:41 +01:00
Clifford Wolf	42d5d94a5d	Added very first version of "synth_ice40"	2015-03-05 20:37:55 +01:00
Clifford Wolf	b005eedf36	Added $assume cell type	2015-02-26 18:04:10 +01:00
Clifford Wolf	4d34d031f9	Added "stat" to "synth" and "synth_xilinx"	2015-02-15 13:25:15 +01:00
Clifford Wolf	881dcd8af9	Added final checks to "synth" and "synth_xilinx"	2015-02-15 13:00:00 +01:00
Clifford Wolf	ec05242c27	Smaller default parameters in $mem simlib model	2015-02-15 00:20:05 +01:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	910556560f	Added $meminit cell type	2015-02-14 10:23:03 +01:00
Clifford Wolf	04cb947d6a	Added "check" command	2015-02-13 14:34:51 +01:00
Clifford Wolf	d58c3eca3a	Some test related fixes ... (incl. removal of three bad test cases)	2015-02-12 17:45:44 +01:00
Clifford Wolf	853e949c0e	Disabled (unused) Xilinx tristate buffers	2015-02-04 16:33:59 +01:00
Clifford Wolf	bebbf2e5a4	no support for 6-series xilinx devices	2015-02-01 23:06:44 +01:00
Clifford Wolf	3cbfa3815e	Removed old XST-based xilinx examples	2015-02-01 17:10:46 +01:00
Clifford Wolf	816fe6bbe0	Added Xilinx example for Basys3 board	2015-02-01 17:09:34 +01:00
Clifford Wolf	1b159bc955	Added missing ports and parameters to xilinx brams	2015-02-01 15:42:59 +01:00
Clifford Wolf	1df81f92ce	Added "make mklibyosys", some minor API changes	2015-02-01 13:38:46 +01:00
Clifford Wolf	bedd46338f	Added "fsm -encfile"	2015-01-30 22:46:53 +01:00
Clifford Wolf	909a95182b	Fixed xilinx FDSE sim model	2015-01-24 11:03:22 +01:00
Clifford Wolf	e13a45ae61	Added $equiv cell type	2015-01-19 11:55:05 +01:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
Clifford Wolf	8d295730e5	Refactoring of memory_bram and xilinx brams	2015-01-18 19:05:29 +01:00
Clifford Wolf	279a18c9a3	Added synth_xilinx -retime -flatten	2015-01-17 20:47:18 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	3ed4e34380	Added cells.lib	2015-01-16 15:50:42 +01:00
Clifford Wolf	dff8bd3b2a	Added dff2dffe to synth_xilinx	2015-01-16 15:49:15 +01:00
Clifford Wolf	7bde74cd2a	Added more FF types to xilinx/cells.v	2015-01-16 15:24:54 +01:00
Clifford Wolf	6b09153320	Fixed xilinx bram clock inverted config	2015-01-16 15:11:56 +01:00
Clifford Wolf	fd8c8d4fd3	Added FF cells to xilinx/cells_sim.v	2015-01-16 14:59:40 +01:00
Clifford Wolf	b197279f3c	Added Xilinx MUXF7 and MUXF8 support	2015-01-15 13:50:04 +01:00
Clifford Wolf	153d3dd4e0	Various cleanups in synth_xilinx command	2015-01-13 13:20:32 +01:00
Clifford Wolf	1d96277f5d	Added add_share_file Makefile macro	2015-01-08 00:23:18 +01:00
Clifford Wolf	38dfc5c580	added minimalistic xilinx sim models	2015-01-08 00:05:11 +01:00
Clifford Wolf	d1e38693d5	More Xilinx bram cleanups	2015-01-07 01:59:36 +01:00
Clifford Wolf	584c5f3937	Cleanups in xilinx bram descriptions	2015-01-07 01:28:18 +01:00
Clifford Wolf	08c13f635c	Xilinx RAMB36/RAMB18 memory_bram support complete	2015-01-06 23:54:33 +01:00
Clifford Wolf	ec2eef89fa	Towards Xilinx bram support	2015-01-06 23:21:52 +01:00
Clifford Wolf	7cc5192125	small fix in xilinx/brams.v	2015-01-06 17:21:18 +01:00
Clifford Wolf	9474928672	Towards Xilinx bram support	2015-01-06 15:26:33 +01:00
Clifford Wolf	4a0b3a5423	Various small improvements to synth_xilinx	2015-01-06 14:37:50 +01:00
Clifford Wolf	081e1a49f8	Towards Xilinx bram support	2015-01-06 14:26:51 +01:00
Clifford Wolf	9c7f47bbd5	Towards Xilinx bram support	2015-01-06 13:33:51 +01:00
Clifford Wolf	9ea2511fe8	Towards Xilinx bram support	2015-01-05 13:59:04 +01:00
Clifford Wolf	8898897f7b	Towards Xilinx bram support	2015-01-04 14:23:30 +01:00
Clifford Wolf	a7e43ae3d9	Progress in memory_bram	2015-01-03 10:57:01 +01:00
Clifford Wolf	90f4017703	Added proper clkpol support to memory_bram	2015-01-02 22:57:08 +01:00
Clifford Wolf	474831643c	New $mem simlib model	2015-01-02 17:11:31 +01:00
Clifford Wolf	327a5d42b6	Progress in memory_bram	2014-12-31 22:50:08 +01:00