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https://github.com/YosysHQ/yosys
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Refactoring of memory_bram and xilinx brams
This commit is contained in:
Clifford Wolf
parent
694cc01f1d
commit
8d295730e5
6 changed files with 496 additions and 704 deletions
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@ -1,133 +1,67 @@
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bram $__XILINX_RAMB36_SDP72
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bram $__XILINX_RAMB36_SDP
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abits 9
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dbits 72
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 8
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transp 2 0
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_SDP36
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bram $__XILINX_RAMB18_SDP
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abits 9
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dbits 36
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 4
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transp 2 0
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP18
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abits 10
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dbits 18
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bram $__XILINX_RAMB18_TDP
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abits 10 @a10d18
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dbits 18 @a10d18
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abits 11 @a11d9
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dbits 9 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 2
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transp 2 0
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enable 0 2 @a10d18
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enable 0 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP9
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abits 11
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dbits 9
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP4
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abits 12
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dbits 4
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP2
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abits 13
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dbits 2
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP1
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abits 14
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__XILINX_RAMB36_SDP72
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match $__XILINX_RAMB36_SDP
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min bits 4096
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min efficiency 5
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shuffle_enable 8
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shuffle_enable B
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP36
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match $__XILINX_RAMB18_SDP
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min bits 4096
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min efficiency 5
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shuffle_enable 4
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shuffle_enable B
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP18
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match $__XILINX_RAMB18_TDP
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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or_next_if_better
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shuffle_enable B
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make_transp
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endmatch
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match $__XILINX_RAMB18_TDP9
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP4
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP2
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP1
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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endmatch
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@ -1,5 +1,4 @@
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module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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@ -19,29 +18,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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wire [7:0] DIP, DOP;
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wire [63:0] DI, DO;
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wire [71:0] A1DATA_BUF;
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reg [71:0] B1DATA_Q;
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reg [7:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
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assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
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assign A1DATA[44:36] = transparent_cycle[4] ? B1DATA_Q[44:36] : A1DATA_BUF[44:36];
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assign A1DATA[53:45] = transparent_cycle[5] ? B1DATA_Q[53:45] : A1DATA_BUF[53:45];
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assign A1DATA[62:54] = transparent_cycle[6] ? B1DATA_Q[62:54] : A1DATA_BUF[62:54];
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assign A1DATA[71:63] = transparent_cycle[7] ? B1DATA_Q[71:63] : A1DATA_BUF[71:63];
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assign A1DATA_BUF = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
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DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
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DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
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DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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@ -84,8 +62,7 @@ endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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@ -105,24 +82,7 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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wire [35:0] A1DATA_BUF;
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reg [35:0] B1DATA_Q;
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reg [3:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
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assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
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assign A1DATA_BUF = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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@ -163,51 +123,40 @@ endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 18;
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parameter CFG_ENABLE_B = 2;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [9:0] A1ADDR;
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output [17:0] A1DATA;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input [9:0] B1ADDR;
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input [17:0] B1DATA;
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input [1:0] B1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 4'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 4'b0};
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wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
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wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
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wire [3:0] B1EN_4 = B1EN;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [17:0] A1DATA_BUF;
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reg [17:0] B1DATA_Q;
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reg [1:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(18),
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.READ_WIDTH_B(18),
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.WRITE_WIDTH_A(18),
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.WRITE_WIDTH_B(18),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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@ -233,307 +182,7 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({2'b00, B1EN})
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [10:0] A1ADDR;
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output [8:0] A1DATA;
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input [10:0] B1ADDR;
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input [8:0] B1DATA;
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input B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0};
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [8:0] A1DATA_BUF;
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reg [8:0] B1DATA_Q;
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reg transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(9),
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.READ_WIDTH_B(9),
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.WRITE_WIDTH_A(9),
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.WRITE_WIDTH_B(9),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({3'b00, B1EN})
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [11:0] A1ADDR;
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output [3:0] A1DATA;
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input [11:0] B1ADDR;
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input [3:0] B1DATA;
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input B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0};
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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reg transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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||||
always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
else
|
||||
always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
endgenerate
|
||||
|
||||
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
|
||||
|
||||
assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(4),
|
||||
.READ_WIDTH_B(4),
|
||||
.WRITE_WIDTH_A(4),
|
||||
.WRITE_WIDTH_B(4),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE({3'b00, B1EN})
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter TRANSP2 = 1;
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [12:0] A1ADDR;
|
||||
output [1:0] A1DATA;
|
||||
|
||||
input [12:0] B1ADDR;
|
||||
input [1:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0};
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [3:0] A1DATA_BUF;
|
||||
reg [3:0] B1DATA_Q;
|
||||
reg transparent_cycle;
|
||||
|
||||
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
|
||||
|
||||
generate if (CLKPOL2)
|
||||
always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
else
|
||||
always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
endgenerate
|
||||
|
||||
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
|
||||
|
||||
assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(2),
|
||||
.READ_WIDTH_B(2),
|
||||
.WRITE_WIDTH_A(2),
|
||||
.WRITE_WIDTH_B(2),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE({3'b00, B1EN})
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter TRANSP2 = 1;
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [13:0] A1ADDR;
|
||||
output A1DATA;
|
||||
|
||||
input [13:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR;
|
||||
wire [13:0] B1ADDR_14 = B1ADDR;
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [3:0] A1DATA_BUF;
|
||||
reg [3:0] B1DATA_Q;
|
||||
reg transparent_cycle;
|
||||
|
||||
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
|
||||
|
||||
generate if (CLKPOL2)
|
||||
always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
else
|
||||
always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
|
||||
endgenerate
|
||||
|
||||
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
|
||||
|
||||
assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(1),
|
||||
.READ_WIDTH_B(1),
|
||||
.WRITE_WIDTH_A(1),
|
||||
.WRITE_WIDTH_B(1),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE({3'b00, B1EN})
|
||||
.WEBWE(B1EN_4)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -2,15 +2,19 @@
|
|||
|
||||
set -e
|
||||
|
||||
transp_list="0 1"
|
||||
abits_list="1 2 4 8 10 16 20"
|
||||
dbits_list="1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80"
|
||||
|
||||
use_xsim=false
|
||||
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
|
||||
|
||||
echo "all: all_list" > bram1.mk
|
||||
all_list=""
|
||||
|
||||
for transp in 0 1; do
|
||||
for abits in 1 2 4 8 10 16 20; do
|
||||
for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
|
||||
for transp in $transp_list; do
|
||||
for abits in $abits_list; do
|
||||
for dbits in $dbits_list; do
|
||||
if [ $(( (1 << $abits) * $dbits )) -gt 1000000 ]; then continue; fi
|
||||
id=`printf "%d%02d%02d" $transp $abits $dbits`
|
||||
echo "Creating bram1_$id.."
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue