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Added $meminit support to "memory" command
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7 changed files with 99 additions and 49 deletions
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@ -1543,6 +1543,7 @@ parameter SIZE = 256;
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parameter OFFSET = 0;
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parameter ABITS = 8;
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parameter WIDTH = 8;
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parameter signed INIT = 1'bx;
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parameter RD_PORTS = 1;
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parameter RD_CLK_ENABLE = 1'b1;
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@ -1583,25 +1584,36 @@ function port_active;
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end
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endfunction
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initial begin
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for (i = 0; i < SIZE; i = i+1)
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memory[i] = INIT >>> (i*WIDTH);
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end
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always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
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`ifdef SIMLIB_MEMDELAY
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#`SIMLIB_MEMDELAY;
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`endif
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
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if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
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// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end
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end
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for (i = 0; i < WR_PORTS; i = i+1) begin
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if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
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for (j = 0; j < WIDTH; j = j+1)
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if (WR_EN[i*WIDTH+j])
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if (WR_EN[i*WIDTH+j]) begin
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// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
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memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
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end
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end
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
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if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
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// $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end
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end
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LAST_RD_CLK <= RD_CLK;
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