Without this check it's trivially easy to crash Yosys with a tiny RTLIL input
by specifying a constant with very large width. Fuzz testers love hitting this
over and over again.
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
Use Bison's typed midrule actions to construct AST_FCALL nodes
with std::unique_ptr, replacing manual 'new' and extra->ast_stack
management. This improves type safety, ensures proper ownership, and
eliminates potential memory leaks.
Ref: https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels. After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:
```
➜ /tmp yosys -p 'read -sv a1.v'
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)
-- Running command `read -sv a1.v' --
1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜ /tmp cat a1.v
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
```
We encountered this issue before but with a different error message[^1],
[^1]: https://github.com/YosysHQ/yosys/issues/862
