mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 21:25:47 +00:00
Update Yosys to latest
This commit is contained in:
Akash Levy
commit
8204fd1d0b
17 changed files with 760 additions and 22 deletions
5
.github/actions/setup-build-env/action.yml
vendored
5
.github/actions/setup-build-env/action.yml
vendored
|
|
@ -14,8 +14,7 @@ runs:
|
|||
if: runner.os == 'macOS'
|
||||
shell: bash
|
||||
run: |
|
||||
HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew update
|
||||
HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew bundle install || true
|
||||
brew bundle
|
||||
|
||||
- name: Linux runtime environment
|
||||
if: runner.os == 'Linux'
|
||||
|
|
@ -29,7 +28,7 @@ runs:
|
|||
shell: bash
|
||||
run: |
|
||||
echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix llvm)/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix llvm@20)/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
|
||||
|
|
|
|||
2
.github/workflows/extra-builds.yml
vendored
2
.github/workflows/extra-builds.yml
vendored
|
|
@ -51,7 +51,7 @@ jobs:
|
|||
uses: microsoft/setup-msbuild@v2
|
||||
- name: MSBuild
|
||||
working-directory: yosys-win32-vcxsrc-latest
|
||||
run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
|
||||
run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.26100.0
|
||||
|
||||
wasi-build:
|
||||
name: WASI build
|
||||
|
|
|
|||
7
.github/workflows/test-compile.yml
vendored
7
.github/workflows/test-compile.yml
vendored
|
|
@ -36,9 +36,12 @@ jobs:
|
|||
- 'clang-19'
|
||||
- 'gcc-13'
|
||||
include:
|
||||
# macOS
|
||||
# macOS x86
|
||||
- os: macos-13
|
||||
compiler: 'clang'
|
||||
compiler: 'clang-19'
|
||||
# macOS arm
|
||||
- os: macos-latest
|
||||
compiler: 'clang-19'
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Checkout Yosys
|
||||
|
|
|
|||
3
Brewfile
3
Brewfile
|
|
@ -6,11 +6,10 @@ brew "git"
|
|||
brew "graphviz"
|
||||
brew "pkg-config"
|
||||
brew "python3"
|
||||
brew "tcl-tk"
|
||||
brew "xdot"
|
||||
brew "bash"
|
||||
brew "boost-python3"
|
||||
brew "llvm"
|
||||
brew "llvm@20"
|
||||
brew "lld"
|
||||
|
||||
brew "autoconf"
|
||||
|
|
|
|||
17
CHANGELOG
17
CHANGELOG
|
|
@ -2,9 +2,24 @@
|
|||
List of major changes and improvements between releases
|
||||
=======================================================
|
||||
|
||||
Yosys 0.56 .. Yosys 0.57-dev
|
||||
Yosys 0.57 .. Yosys 0.58-dev
|
||||
--------------------------
|
||||
|
||||
Yosys 0.56 .. Yosys 0.57
|
||||
--------------------------
|
||||
* New commands and options
|
||||
- Added "-initstates" option to "abstract" pass.
|
||||
- Added "-set-assumes" option to "equiv_induct"
|
||||
and "equiv_simple" passes.
|
||||
- Added "-always" option to "raise_error" pass.
|
||||
- Added "-hierarchy" option to "stat" pass.
|
||||
- Added "-noflatten" option to "synth_quicklogic" pass.
|
||||
|
||||
* Various
|
||||
- smtbmc: Support skipping steps in cover mode.
|
||||
- write_btor: support $buf.
|
||||
- read_verilog: support package import.
|
||||
|
||||
Yosys 0.55 .. Yosys 0.56
|
||||
--------------------------
|
||||
* New commands and options
|
||||
|
|
|
|||
4
Makefile
4
Makefile
|
|
@ -175,7 +175,7 @@ ifeq ($(OS), Haiku)
|
|||
CXXFLAGS += -D_DEFAULT_SOURCE
|
||||
endif
|
||||
|
||||
YOSYS_VER := 0.56+186
|
||||
YOSYS_VER := 0.57+7
|
||||
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
|
||||
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
|
||||
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
|
||||
|
|
@ -198,7 +198,7 @@ endif
|
|||
OBJS = kernel/version_$(GIT_REV).o
|
||||
|
||||
bumpversion:
|
||||
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9c447ad.. | wc -l`/;" Makefile
|
||||
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 3aca860.. | wc -l`/;" Makefile
|
||||
|
||||
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
|
||||
|
||||
|
|
|
|||
2
abc
2
abc
|
|
@ -1 +1 @@
|
|||
Subproject commit 9bff4a1642991d968ef43322543cff1187891387
|
||||
Subproject commit aa6a0af59bc08450722040e08d74b29fad9b9f49
|
||||
|
|
@ -509,7 +509,7 @@ struct BtorWorker
|
|||
goto okay;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos)))
|
||||
if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
|
||||
{
|
||||
string btor_op;
|
||||
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
|
||||
|
|
@ -521,9 +521,9 @@ struct BtorWorker
|
|||
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
|
||||
SigSpec sig = sigmap(cell->getPort(ID::Y));
|
||||
|
||||
// the $pos cell just passes through, all other cells need an actual operation applied
|
||||
// the $pos/$buf cells just pass through, all other cells need an actual operation applied
|
||||
int nid = nid_a;
|
||||
if (cell->type != ID($pos))
|
||||
if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_)))
|
||||
{
|
||||
log_assert(!btor_op.empty());
|
||||
int sid = get_bv_sid(width);
|
||||
|
|
|
|||
|
|
@ -1875,6 +1875,11 @@ elif covermode:
|
|||
smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, step-1, step))
|
||||
smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, step))
|
||||
|
||||
if step < skip_steps:
|
||||
print_msg("Skipping step %d.." % (step))
|
||||
step += 1
|
||||
continue
|
||||
|
||||
while "1" in cover_mask:
|
||||
print_msg("Checking cover reachability in step %d.." % (step))
|
||||
smt_push()
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ import os
|
|||
project = 'YosysHQ Yosys'
|
||||
author = 'YosysHQ GmbH'
|
||||
copyright ='2025 YosysHQ GmbH'
|
||||
yosys_ver = "0.56"
|
||||
yosys_ver = "0.57"
|
||||
|
||||
# select HTML theme
|
||||
html_theme = 'furo-ys'
|
||||
|
|
|
|||
|
|
@ -3023,7 +3023,8 @@ case_expr_list:
|
|||
SET_AST_NODE_LOC(node, @1, @1);
|
||||
} |
|
||||
TOK_SVA_LABEL {
|
||||
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
|
||||
AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
|
||||
node->str = *$1;
|
||||
SET_AST_NODE_LOC(node, @1, @1);
|
||||
} |
|
||||
expr {
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ struct ContextData {
|
|||
std::string unused_outputs;
|
||||
};
|
||||
|
||||
std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters,
|
||||
std::optional<std::string> format_with_params(std::string fmt, const dict<IdString, Const> ¶meters,
|
||||
const ContextData &context)
|
||||
{
|
||||
std::stringstream result;
|
||||
|
|
@ -230,7 +230,7 @@ struct WrapcellPass : Pass {
|
|||
context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
|
||||
}
|
||||
|
||||
std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters, context);
|
||||
std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
|
||||
if (!unescaped_name)
|
||||
log_error("Formatting error when processing cell '%s' in module '%s'\n",
|
||||
log_id(cell), log_id(module));
|
||||
|
|
@ -270,7 +270,7 @@ struct WrapcellPass : Pass {
|
|||
if (rule.value_fmt.empty()) {
|
||||
subm->set_bool_attribute(rule.name);
|
||||
} else {
|
||||
std::optional<std::string> value = format(rule.value_fmt, cell->parameters, context);
|
||||
std::optional<std::string> value = format_with_params(rule.value_fmt, cell->parameters, context);
|
||||
|
||||
if (!value)
|
||||
log_error("Formatting error when processing cell '%s' in module '%s'\n",
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ struct OptDffWorker
|
|||
|
||||
const auto complimentary_var = find_comp(left, right);
|
||||
|
||||
if (complimentary_var) {
|
||||
if (complimentary_var && new_patterns.count(right)) {
|
||||
new_patterns.erase(right);
|
||||
right.erase(complimentary_var.value());
|
||||
new_patterns.insert(right);
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ struct OptMuxtreeWorker
|
|||
RTLIL::Module *module;
|
||||
SigMap assign_map;
|
||||
int removed_count;
|
||||
int glob_evals_left = 100000;
|
||||
int glob_evals_left = 10000000;
|
||||
|
||||
struct bitinfo_t {
|
||||
// Is bit directly used by non-mux cells or ports?
|
||||
|
|
|
|||
648
tests/opt/opt_dff-simplify.il
Normal file
648
tests/opt/opt_dff-simplify.il
Normal file
|
|
@ -0,0 +1,648 @@
|
|||
# Generated by Yosys 0.53+24 (git sha1 ab636979e, sccache clang++ 19.1.7 -fPIC -O3 -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=address,undefined)
|
||||
autoidx 171528
|
||||
attribute \hdlname "csr_regfile_0000000000000000_1"
|
||||
module \csr_regfile_0000000000000000_1
|
||||
wire $delete_wire$169641
|
||||
wire $delete_wire$169642
|
||||
wire $delete_wire$169643
|
||||
wire $delete_wire$169644
|
||||
wire $delete_wire$169645
|
||||
wire $delete_wire$169646
|
||||
wire $delete_wire$169647
|
||||
wire $delete_wire$169648
|
||||
wire $delete_wire$169649
|
||||
wire $delete_wire$169650
|
||||
wire $delete_wire$169651
|
||||
wire $delete_wire$169652
|
||||
wire $delete_wire$169653
|
||||
wire $delete_wire$169654
|
||||
wire $delete_wire$169655
|
||||
wire $delete_wire$169656
|
||||
wire $delete_wire$169657
|
||||
wire $delete_wire$169658
|
||||
wire $delete_wire$169659
|
||||
wire $delete_wire$169660
|
||||
wire $delete_wire$169661
|
||||
wire $delete_wire$169662
|
||||
wire $delete_wire$169663
|
||||
wire $delete_wire$169664
|
||||
wire $delete_wire$169665
|
||||
wire $delete_wire$169666
|
||||
wire $delete_wire$169667
|
||||
wire $delete_wire$169668
|
||||
wire $delete_wire$169669
|
||||
wire $delete_wire$169670
|
||||
wire $delete_wire$169671
|
||||
wire $delete_wire$169672
|
||||
wire $delete_wire$169673
|
||||
wire $delete_wire$169674
|
||||
wire $delete_wire$169675
|
||||
wire $delete_wire$169676
|
||||
wire $delete_wire$169677
|
||||
wire $delete_wire$169678
|
||||
wire $delete_wire$169679
|
||||
wire $delete_wire$169680
|
||||
wire $delete_wire$169681
|
||||
wire $delete_wire$169682
|
||||
wire $delete_wire$169683
|
||||
wire $delete_wire$169684
|
||||
wire $delete_wire$169685
|
||||
wire $delete_wire$169686
|
||||
wire $delete_wire$169687
|
||||
wire $delete_wire$169688
|
||||
wire $delete_wire$169689
|
||||
wire $delete_wire$169690
|
||||
wire $delete_wire$169691
|
||||
wire $delete_wire$169692
|
||||
wire $delete_wire$169693
|
||||
wire $delete_wire$169694
|
||||
wire $delete_wire$169695
|
||||
wire $delete_wire$169696
|
||||
wire $delete_wire$169697
|
||||
wire $delete_wire$169698
|
||||
wire $delete_wire$169699
|
||||
wire $delete_wire$169700
|
||||
wire $delete_wire$169701
|
||||
wire $delete_wire$169702
|
||||
wire $delete_wire$169703
|
||||
wire $delete_wire$169704
|
||||
wire $delete_wire$169705
|
||||
wire $delete_wire$169706
|
||||
wire $delete_wire$169707
|
||||
wire $delete_wire$169708
|
||||
wire $delete_wire$169709
|
||||
wire $delete_wire$169710
|
||||
wire $delete_wire$169711
|
||||
wire $delete_wire$169712
|
||||
wire width 32 $delete_wire$169713
|
||||
wire $delete_wire$169714
|
||||
wire $delete_wire$169715
|
||||
wire $delete_wire$169716
|
||||
wire $delete_wire$169717
|
||||
wire $delete_wire$169718
|
||||
wire $delete_wire$169719
|
||||
wire $delete_wire$169720
|
||||
wire $delete_wire$169721
|
||||
wire $delete_wire$169722
|
||||
wire $delete_wire$169723
|
||||
wire $delete_wire$169724
|
||||
wire $delete_wire$169725
|
||||
wire $delete_wire$169726
|
||||
wire $delete_wire$169727
|
||||
wire $delete_wire$169728
|
||||
wire $delete_wire$169729
|
||||
wire $delete_wire$169730
|
||||
wire $delete_wire$169731
|
||||
wire $delete_wire$169732
|
||||
wire $delete_wire$169733
|
||||
wire $delete_wire$169734
|
||||
wire $delete_wire$169735
|
||||
wire $delete_wire$169736
|
||||
wire $delete_wire$169737
|
||||
wire $delete_wire$169738
|
||||
wire $delete_wire$169739
|
||||
wire $delete_wire$169740
|
||||
wire $delete_wire$169741
|
||||
wire $delete_wire$169742
|
||||
wire $delete_wire$169743
|
||||
wire $delete_wire$169744
|
||||
wire $delete_wire$169745
|
||||
wire $delete_wire$169746
|
||||
wire $delete_wire$169747
|
||||
wire $delete_wire$169748
|
||||
wire $delete_wire$169749
|
||||
wire $delete_wire$169750
|
||||
wire $delete_wire$169751
|
||||
wire $delete_wire$169752
|
||||
wire $delete_wire$169753
|
||||
wire $delete_wire$169754
|
||||
wire $delete_wire$169755
|
||||
wire $delete_wire$169756
|
||||
wire $delete_wire$169757
|
||||
wire $delete_wire$169758
|
||||
wire $delete_wire$169759
|
||||
wire $delete_wire$169760
|
||||
wire $delete_wire$169761
|
||||
wire $delete_wire$169762
|
||||
wire $delete_wire$169763
|
||||
wire $delete_wire$169764
|
||||
wire $delete_wire$169765
|
||||
wire $delete_wire$169766
|
||||
wire $delete_wire$169767
|
||||
wire $delete_wire$169768
|
||||
wire $delete_wire$169769
|
||||
wire $delete_wire$169770
|
||||
wire $delete_wire$169771
|
||||
wire $delete_wire$169772
|
||||
wire $delete_wire$169773
|
||||
wire $delete_wire$169774
|
||||
wire $delete_wire$169775
|
||||
wire $delete_wire$169776
|
||||
wire $delete_wire$169777
|
||||
wire $delete_wire$169778
|
||||
wire $delete_wire$169779
|
||||
wire $delete_wire$169780
|
||||
wire $delete_wire$169781
|
||||
wire $delete_wire$169782
|
||||
wire $delete_wire$169783
|
||||
wire $delete_wire$169784
|
||||
wire $delete_wire$169785
|
||||
wire $delete_wire$169786
|
||||
wire $delete_wire$169787
|
||||
wire $delete_wire$169788
|
||||
wire $delete_wire$169789
|
||||
wire $delete_wire$169790
|
||||
wire $delete_wire$169791
|
||||
wire $delete_wire$169792
|
||||
wire $delete_wire$169793
|
||||
wire $delete_wire$169794
|
||||
wire $delete_wire$169795
|
||||
wire $delete_wire$169796
|
||||
wire $delete_wire$169797
|
||||
wire $delete_wire$169798
|
||||
wire $delete_wire$169799
|
||||
wire $delete_wire$169800
|
||||
wire $delete_wire$169801
|
||||
wire $delete_wire$169802
|
||||
wire $delete_wire$169803
|
||||
wire $delete_wire$169804
|
||||
wire $delete_wire$169805
|
||||
wire $delete_wire$169806
|
||||
wire $delete_wire$169807
|
||||
wire $delete_wire$169808
|
||||
wire $delete_wire$169809
|
||||
wire $delete_wire$169810
|
||||
wire $delete_wire$169811
|
||||
wire $delete_wire$169812
|
||||
wire $delete_wire$169813
|
||||
wire $delete_wire$169814
|
||||
wire $delete_wire$169815
|
||||
wire $delete_wire$169816
|
||||
wire $delete_wire$169817
|
||||
wire $delete_wire$169818
|
||||
wire $delete_wire$169819
|
||||
wire $delete_wire$169820
|
||||
wire $delete_wire$169821
|
||||
wire width 5 $delete_wire$169822
|
||||
wire width 17 $delete_wire$169823
|
||||
wire $delete_wire$169824
|
||||
wire $delete_wire$169825
|
||||
wire $delete_wire$169826
|
||||
wire $delete_wire$169827
|
||||
wire $delete_wire$169828
|
||||
wire $delete_wire$169829
|
||||
wire $delete_wire$169830
|
||||
wire $delete_wire$169831
|
||||
wire $delete_wire$169832
|
||||
wire $delete_wire$169833
|
||||
wire $delete_wire$169834
|
||||
wire $delete_wire$169835
|
||||
wire $delete_wire$169836
|
||||
wire $delete_wire$169837
|
||||
wire $delete_wire$169838
|
||||
wire $delete_wire$169839
|
||||
wire $delete_wire$169840
|
||||
wire $delete_wire$169960
|
||||
wire $delete_wire$169961
|
||||
wire $delete_wire$169962
|
||||
wire $delete_wire$169963
|
||||
wire $delete_wire$169964
|
||||
wire $delete_wire$169965
|
||||
wire $delete_wire$169966
|
||||
wire $delete_wire$169967
|
||||
wire $delete_wire$169968
|
||||
wire $delete_wire$169969
|
||||
wire $delete_wire$169970
|
||||
wire $delete_wire$169971
|
||||
wire $delete_wire$169972
|
||||
wire $delete_wire$169973
|
||||
wire $delete_wire$169974
|
||||
wire $delete_wire$169975
|
||||
wire $delete_wire$169976
|
||||
wire $delete_wire$169977
|
||||
wire $delete_wire$169978
|
||||
wire $delete_wire$169979
|
||||
wire $delete_wire$169980
|
||||
wire $delete_wire$169981
|
||||
wire $delete_wire$169982
|
||||
wire $delete_wire$169983
|
||||
wire $delete_wire$169984
|
||||
wire $delete_wire$169985
|
||||
wire $delete_wire$169986
|
||||
wire $delete_wire$169987
|
||||
wire $delete_wire$169988
|
||||
wire $delete_wire$169989
|
||||
wire $delete_wire$169990
|
||||
wire $delete_wire$169991
|
||||
wire $delete_wire$169992
|
||||
wire $delete_wire$169993
|
||||
wire $delete_wire$169994
|
||||
wire $delete_wire$169995
|
||||
wire $delete_wire$169996
|
||||
wire $delete_wire$169997
|
||||
wire $delete_wire$169998
|
||||
wire $delete_wire$169999
|
||||
wire $delete_wire$170000
|
||||
wire $delete_wire$170001
|
||||
wire $delete_wire$170002
|
||||
wire $delete_wire$170003
|
||||
wire $delete_wire$170004
|
||||
wire $delete_wire$170005
|
||||
wire $delete_wire$170006
|
||||
wire $delete_wire$170007
|
||||
wire $delete_wire$170008
|
||||
wire $delete_wire$170009
|
||||
wire $delete_wire$170010
|
||||
wire $delete_wire$170011
|
||||
wire $delete_wire$170012
|
||||
wire $delete_wire$170013
|
||||
wire $delete_wire$170014
|
||||
wire $delete_wire$170015
|
||||
wire $delete_wire$170016
|
||||
wire $delete_wire$170017
|
||||
wire $delete_wire$170018
|
||||
wire $delete_wire$170019
|
||||
wire $delete_wire$170020
|
||||
wire $delete_wire$170021
|
||||
wire $delete_wire$170022
|
||||
wire $delete_wire$170023
|
||||
wire $delete_wire$170024
|
||||
wire $delete_wire$170025
|
||||
wire $delete_wire$170026
|
||||
wire $delete_wire$170027
|
||||
wire $delete_wire$170028
|
||||
wire $delete_wire$170029
|
||||
wire $delete_wire$170030
|
||||
wire $delete_wire$170031
|
||||
wire $delete_wire$170032
|
||||
wire $delete_wire$170033
|
||||
wire $delete_wire$170034
|
||||
wire $delete_wire$170035
|
||||
wire $delete_wire$170036
|
||||
wire $delete_wire$170037
|
||||
wire $delete_wire$170038
|
||||
wire $delete_wire$170039
|
||||
wire $delete_wire$170040
|
||||
wire $delete_wire$170041
|
||||
wire $delete_wire$170042
|
||||
wire $delete_wire$170043
|
||||
wire $delete_wire$170044
|
||||
wire $delete_wire$170045
|
||||
wire $delete_wire$170046
|
||||
wire $delete_wire$170047
|
||||
wire $delete_wire$170048
|
||||
wire $delete_wire$170049
|
||||
wire $delete_wire$170050
|
||||
wire $delete_wire$170051
|
||||
wire $delete_wire$170052
|
||||
wire $delete_wire$170053
|
||||
wire $delete_wire$170054
|
||||
wire $delete_wire$170055
|
||||
wire $delete_wire$170056
|
||||
wire $delete_wire$170057
|
||||
wire $delete_wire$170058
|
||||
wire $delete_wire$170059
|
||||
wire $delete_wire$170635
|
||||
wire $delete_wire$170636
|
||||
wire $delete_wire$170637
|
||||
wire $delete_wire$170638
|
||||
wire $delete_wire$170639
|
||||
wire $delete_wire$170640
|
||||
wire $delete_wire$170641
|
||||
wire $delete_wire$170642
|
||||
wire $delete_wire$170643
|
||||
wire $delete_wire$170644
|
||||
wire $delete_wire$170645
|
||||
wire $delete_wire$170646
|
||||
wire $delete_wire$170647
|
||||
wire $delete_wire$170648
|
||||
wire $delete_wire$170649
|
||||
wire $delete_wire$170650
|
||||
wire $delete_wire$170651
|
||||
wire $delete_wire$170652
|
||||
wire $delete_wire$170653
|
||||
wire $delete_wire$170654
|
||||
wire $delete_wire$170655
|
||||
wire $delete_wire$170656
|
||||
wire $delete_wire$170657
|
||||
wire $delete_wire$170658
|
||||
wire $delete_wire$170659
|
||||
wire $delete_wire$170660
|
||||
wire $delete_wire$170661
|
||||
wire $delete_wire$170662
|
||||
wire $delete_wire$170663
|
||||
wire $delete_wire$170664
|
||||
wire $delete_wire$170665
|
||||
wire $delete_wire$170666
|
||||
wire $delete_wire$170667
|
||||
wire $delete_wire$170668
|
||||
wire $delete_wire$170669
|
||||
wire $delete_wire$170670
|
||||
wire $delete_wire$170749
|
||||
wire $delete_wire$170750
|
||||
wire $delete_wire$170751
|
||||
wire $delete_wire$170752
|
||||
wire $delete_wire$170753
|
||||
wire $delete_wire$170754
|
||||
wire $delete_wire$170755
|
||||
wire width 2 $delete_wire$170756
|
||||
wire width 2 $delete_wire$170757
|
||||
wire $delete_wire$170758
|
||||
wire $delete_wire$170759
|
||||
wire $delete_wire$170760
|
||||
wire $delete_wire$170761
|
||||
wire $delete_wire$170762
|
||||
wire $delete_wire$170763
|
||||
wire $delete_wire$170764
|
||||
wire $delete_wire$170765
|
||||
wire $delete_wire$170766
|
||||
wire $delete_wire$170767
|
||||
wire $delete_wire$170768
|
||||
wire $delete_wire$170769
|
||||
wire $delete_wire$170770
|
||||
wire $delete_wire$170771
|
||||
wire $delete_wire$170772
|
||||
wire $delete_wire$170773
|
||||
wire $delete_wire$170774
|
||||
wire $delete_wire$170775
|
||||
wire $delete_wire$170859
|
||||
wire $delete_wire$170860
|
||||
wire $delete_wire$170861
|
||||
wire $delete_wire$170862
|
||||
wire $delete_wire$170863
|
||||
wire $delete_wire$170864
|
||||
wire $delete_wire$170865
|
||||
wire $delete_wire$170866
|
||||
wire $delete_wire$170867
|
||||
wire $delete_wire$170868
|
||||
wire $delete_wire$170869
|
||||
wire $delete_wire$170870
|
||||
wire $delete_wire$170871
|
||||
wire $delete_wire$170872
|
||||
wire $delete_wire$170873
|
||||
wire $delete_wire$170874
|
||||
wire $delete_wire$170875
|
||||
wire $delete_wire$170876
|
||||
wire $delete_wire$170877
|
||||
wire $delete_wire$170878
|
||||
wire $delete_wire$170879
|
||||
wire $delete_wire$170880
|
||||
wire $delete_wire$170881
|
||||
wire $delete_wire$170882
|
||||
wire $delete_wire$170996
|
||||
wire $delete_wire$170997
|
||||
wire $delete_wire$170998
|
||||
wire $delete_wire$170999
|
||||
wire $delete_wire$171000
|
||||
wire $delete_wire$171001
|
||||
wire $delete_wire$171002
|
||||
wire $delete_wire$171003
|
||||
wire $delete_wire$171004
|
||||
wire $delete_wire$171005
|
||||
wire $delete_wire$171006
|
||||
wire $delete_wire$171007
|
||||
wire $delete_wire$171008
|
||||
wire $delete_wire$171009
|
||||
wire $delete_wire$171010
|
||||
wire $delete_wire$171011
|
||||
wire $delete_wire$171035
|
||||
wire $delete_wire$171036
|
||||
wire $delete_wire$171037
|
||||
wire $delete_wire$171038
|
||||
wire $delete_wire$171039
|
||||
wire $delete_wire$171040
|
||||
wire $delete_wire$171041
|
||||
wire $delete_wire$171042
|
||||
wire $delete_wire$171043
|
||||
wire $delete_wire$171044
|
||||
wire $delete_wire$171045
|
||||
wire $delete_wire$171046
|
||||
wire $delete_wire$171047
|
||||
wire $delete_wire$171048
|
||||
wire $delete_wire$171049
|
||||
wire $delete_wire$171172
|
||||
wire $delete_wire$171173
|
||||
wire $delete_wire$171174
|
||||
wire $delete_wire$171175
|
||||
wire $delete_wire$171176
|
||||
wire $delete_wire$171177
|
||||
wire $delete_wire$171178
|
||||
wire $delete_wire$171179
|
||||
wire $delete_wire$171180
|
||||
wire $delete_wire$171181
|
||||
wire $delete_wire$171182
|
||||
wire $delete_wire$171183
|
||||
wire $delete_wire$171184
|
||||
wire $delete_wire$171185
|
||||
wire $delete_wire$171186
|
||||
wire $delete_wire$171187
|
||||
wire $delete_wire$171188
|
||||
wire $delete_wire$171189
|
||||
wire $delete_wire$171190
|
||||
wire width 2 $delete_wire$171200
|
||||
wire width 2 $delete_wire$171201
|
||||
wire $delete_wire$171202
|
||||
wire $delete_wire$171203
|
||||
wire $delete_wire$171204
|
||||
wire $delete_wire$171205
|
||||
wire $delete_wire$171206
|
||||
wire $delete_wire$171207
|
||||
wire $delete_wire$171226
|
||||
wire $delete_wire$171227
|
||||
wire $delete_wire$171228
|
||||
wire $delete_wire$171229
|
||||
wire $delete_wire$171230
|
||||
wire $delete_wire$171231
|
||||
wire $delete_wire$171232
|
||||
wire $delete_wire$171254
|
||||
wire $delete_wire$171255
|
||||
wire $delete_wire$171256
|
||||
wire $delete_wire$171257
|
||||
wire $delete_wire$171258
|
||||
wire $delete_wire$171259
|
||||
wire $delete_wire$171267
|
||||
wire $delete_wire$171268
|
||||
wire $delete_wire$171269
|
||||
wire $delete_wire$171270
|
||||
wire $delete_wire$171271
|
||||
wire $delete_wire$171272
|
||||
wire $delete_wire$171314
|
||||
wire $delete_wire$171315
|
||||
wire $delete_wire$171316
|
||||
wire $delete_wire$171317
|
||||
wire $delete_wire$171318
|
||||
wire $delete_wire$171338
|
||||
wire $delete_wire$171339
|
||||
wire $delete_wire$171340
|
||||
wire $delete_wire$171341
|
||||
wire $delete_wire$171350
|
||||
wire $delete_wire$171351
|
||||
wire $delete_wire$171352
|
||||
wire $delete_wire$171353
|
||||
wire $delete_wire$171354
|
||||
wire $delete_wire$171355
|
||||
wire $delete_wire$171356
|
||||
wire $delete_wire$171357
|
||||
wire $delete_wire$171358
|
||||
wire $delete_wire$171359
|
||||
wire $delete_wire$171360
|
||||
wire width 2 $delete_wire$171361
|
||||
wire $delete_wire$171362
|
||||
wire $delete_wire$171371
|
||||
wire $delete_wire$171372
|
||||
wire $delete_wire$171373
|
||||
wire $delete_wire$171374
|
||||
wire $delete_wire$171387
|
||||
wire $delete_wire$171388
|
||||
wire $delete_wire$171389
|
||||
wire $delete_wire$171390
|
||||
wire $delete_wire$171408
|
||||
wire $delete_wire$171409
|
||||
wire $delete_wire$171441
|
||||
wire $delete_wire$171442
|
||||
wire $delete_wire$171449
|
||||
wire $delete_wire$171450
|
||||
wire $delete_wire$171454
|
||||
wire $delete_wire$171455
|
||||
wire $delete_wire$171471
|
||||
wire $delete_wire$171472
|
||||
wire $delete_wire$171477
|
||||
wire $delete_wire$171501
|
||||
wire $delete_wire$171502
|
||||
wire $delete_wire$171507
|
||||
wire $delete_wire$171512
|
||||
wire $delete_wire$171513
|
||||
wire $delete_wire$171514
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
|
||||
wire width 32 $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
|
||||
wire \N2231
|
||||
wire \N3558
|
||||
attribute \unused_bits "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31"
|
||||
wire width 32 \dcsr_d
|
||||
wire \dcsr_q_prv__0_
|
||||
cell $adff $procdff$137332
|
||||
parameter \ARST_POLARITY 0
|
||||
parameter \ARST_VALUE 1'1
|
||||
parameter \CLK_POLARITY 1'1
|
||||
parameter \WIDTH 1
|
||||
connect \ARST $delete_wire$170004
|
||||
connect \CLK $delete_wire$171206
|
||||
connect \D \dcsr_d [0]
|
||||
connect \Q \dcsr_q_prv__0_
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216087$6334
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$170875 $delete_wire$171472 $delete_wire$171181 $delete_wire$169735 $delete_wire$169994 $delete_wire$169963 $delete_wire$170670 $delete_wire$169702 $delete_wire$169975 $delete_wire$170002 $delete_wire$169641 $delete_wire$171011 $delete_wire$171006 $delete_wire$171173 $delete_wire$171387 $delete_wire$170769 $delete_wire$170881 $delete_wire$169743 $delete_wire$169731 $delete_wire$169710 $delete_wire$169756 $delete_wire$170018 $delete_wire$169779 $delete_wire$170037 $delete_wire$169794 $delete_wire$171339 $delete_wire$171256 $delete_wire$171205 $delete_wire$169670 $delete_wire$171352 $delete_wire$171315 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
|
||||
connect \S $delete_wire$169809
|
||||
connect \Y { $delete_wire$169830 $delete_wire$171390 $delete_wire$169837 $delete_wire$169679 $delete_wire$169677 $delete_wire$169767 $delete_wire$169828 $delete_wire$170038 $delete_wire$169704 $delete_wire$169653 $delete_wire$169707 $delete_wire$169684 $delete_wire$169986 $delete_wire$169712 $delete_wire$170033 $delete_wire$169759 $delete_wire$171513 $delete_wire$170012 $delete_wire$170876 $delete_wire$170007 $delete_wire$169965 $delete_wire$169825 $delete_wire$169655 $delete_wire$169839 $delete_wire$170034 $delete_wire$170042 $delete_wire$171338 $delete_wire$169833 $delete_wire$169762 $delete_wire$169835 $delete_wire$169764 \N2231 }
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$170014 $delete_wire$171257 $delete_wire$170770 $delete_wire$169725 $delete_wire$170873 $delete_wire$171514 $delete_wire$170870 $delete_wire$169692 $delete_wire$171184 $delete_wire$170045 $delete_wire$169649 $delete_wire$170859 $delete_wire$171455 $delete_wire$170053 $delete_wire$170044 $delete_wire$170768 $delete_wire$170659 $delete_wire$169742 $delete_wire$169730 $delete_wire$169718 $delete_wire$169741 $delete_wire$170019 $delete_wire$169778 $delete_wire$170024 $delete_wire$169807 $delete_wire$171046 $delete_wire$171374 $delete_wire$170861 $delete_wire$169669 $delete_wire$171182 $delete_wire$171388 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
|
||||
connect \S $delete_wire$169810
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216088$6333_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169820 $delete_wire$171507 $delete_wire$171441 $delete_wire$169724 $delete_wire$169992 $delete_wire$169691 $delete_wire$171356 $delete_wire$169700 $delete_wire$169977 $delete_wire$170046 $delete_wire$169648 $delete_wire$170774 $delete_wire$171038 $delete_wire$171005 $delete_wire$170057 $delete_wire$171226 $delete_wire$170874 $delete_wire$169755 $delete_wire$169729 $delete_wire$171450 $delete_wire$169754 $delete_wire$170020 $delete_wire$169777 $delete_wire$170025 $delete_wire$169806 $delete_wire$170643 $delete_wire$171177 $delete_wire$171449 $delete_wire$169668 $delete_wire$171512 $delete_wire$171501 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
|
||||
connect \S $delete_wire$169997
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216089$6332_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169819 $delete_wire$170772 $delete_wire$170773 $delete_wire$169723 $delete_wire$169990 $delete_wire$169690 $delete_wire$170669 $delete_wire$169699 $delete_wire$169978 $delete_wire$170047 $delete_wire$169647 $delete_wire$171049 $delete_wire$171007 $delete_wire$170872 $delete_wire$170056 $delete_wire$171004 $delete_wire$171202 $delete_wire$169793 $delete_wire$169728 $delete_wire$170664 $delete_wire$169753 $delete_wire$170021 $delete_wire$169776 $delete_wire$170026 $delete_wire$169805 $delete_wire$170644 $delete_wire$171008 $delete_wire$170657 $delete_wire$169658 $delete_wire$171003 $delete_wire$170749 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
|
||||
connect \S $delete_wire$169826
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216090$6331_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330
|
||||
parameter \WIDTH 32
|
||||
connect \A { 4'0100 $delete_wire$169823 2'00 $delete_wire$169822 1'0 $delete_wire$169781 $delete_wire$170757 }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
|
||||
connect \S $delete_wire$170006
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216091$6330_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169818 $delete_wire$170762 $delete_wire$170868 $delete_wire$169722 $delete_wire$169991 $delete_wire$169689 $delete_wire$170642 $delete_wire$169698 $delete_wire$169979 $delete_wire$170048 $delete_wire$169646 $delete_wire$171409 $delete_wire$171259 $delete_wire$170043 $delete_wire$170055 $delete_wire$171471 $delete_wire$170646 $delete_wire$169792 $delete_wire$169727 $delete_wire$169740 $delete_wire$169752 $delete_wire$170022 $delete_wire$169775 $delete_wire$170027 $delete_wire$169804 $delete_wire$170666 $delete_wire$170663 $delete_wire$171179 $delete_wire$169666 $delete_wire$171186 $delete_wire$170655 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
|
||||
connect \S $delete_wire$169972
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216092$6329_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169817 $delete_wire$171190 $delete_wire$171408 $delete_wire$169721 $delete_wire$171002 $delete_wire$169688 $delete_wire$171270 $delete_wire$169697 $delete_wire$169980 $delete_wire$169982 $delete_wire$169645 $delete_wire$171180 $delete_wire$169771 $delete_wire$170860 $delete_wire$170054 $delete_wire$171009 $delete_wire$170639 $delete_wire$169791 $delete_wire$170879 $delete_wire$169739 $delete_wire$169751 $delete_wire$170049 $delete_wire$169774 $delete_wire$170028 $delete_wire$169803 $delete_wire$170645 $delete_wire$169989 $delete_wire$171272 $delete_wire$169665 $delete_wire$171174 $delete_wire$170653 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
|
||||
connect \S $delete_wire$170036
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216093$6328_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169816 $delete_wire$171228 $delete_wire$171454 $delete_wire$169720 $delete_wire$170997 $delete_wire$169687 $delete_wire$170649 $delete_wire$169696 $delete_wire$169981 $delete_wire$170050 $delete_wire$169644 $delete_wire$170760 $delete_wire$169786 $delete_wire$170862 $delete_wire$170032 $delete_wire$171389 $delete_wire$171043 $delete_wire$169790 $delete_wire$169749 $delete_wire$169738 $delete_wire$169750 $delete_wire$169983 $delete_wire$169773 $delete_wire$170029 $delete_wire$169802 $delete_wire$170660 $delete_wire$169962 $delete_wire$170658 $delete_wire$169664 $delete_wire$170751 $delete_wire$170640 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
|
||||
connect \S $delete_wire$169705
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216094$6327_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169815 $delete_wire$171372 $delete_wire$171175 $delete_wire$169719 $delete_wire$171044 $delete_wire$169686 $delete_wire$171231 $delete_wire$169695 $delete_wire$170008 $delete_wire$170052 $delete_wire$169643 $delete_wire$170996 $delete_wire$169785 $delete_wire$170865 $delete_wire$170636 $delete_wire$171185 $delete_wire$171188 $delete_wire$169789 $delete_wire$171045 $delete_wire$169737 $delete_wire$169765 $delete_wire$171268 $delete_wire$169772 $delete_wire$170016 $delete_wire$169801 $delete_wire$170665 $delete_wire$170058 $delete_wire$169961 $delete_wire$169663 $delete_wire$171502 $delete_wire$170652 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
|
||||
connect \S $delete_wire$170650
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216095$6326_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169814 $delete_wire$170753 $delete_wire$171176 $delete_wire$169709 $delete_wire$170999 $delete_wire$169685 $delete_wire$170647 $delete_wire$169694 $delete_wire$169999 $delete_wire$170051 $delete_wire$169642 $delete_wire$170863 $delete_wire$169784 $delete_wire$170755 $delete_wire$170754 $delete_wire$171204 $delete_wire$171373 $delete_wire$169788 $delete_wire$170059 $delete_wire$169736 $delete_wire$169748 $delete_wire$171351 $delete_wire$169787 $delete_wire$171340 $delete_wire$169800 $delete_wire$170638 $delete_wire$169970 $delete_wire$169974 $delete_wire$169662 $delete_wire$170764 $delete_wire$170651 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
|
||||
connect \S $delete_wire$169996
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216096$6325_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169813 $delete_wire$171229 $delete_wire$170765 $delete_wire$169717 $delete_wire$171035 $delete_wire$169675 $delete_wire$170637 $delete_wire$169693 $delete_wire$170000 $delete_wire$171000 $delete_wire$169650 $delete_wire$171442 $delete_wire$169783 $delete_wire$170882 $delete_wire$171318 $delete_wire$171010 $delete_wire$171357 $delete_wire$169821 $delete_wire$170880 $delete_wire$169726 $delete_wire$169747 $delete_wire$169984 $delete_wire$169770 $delete_wire$170031 $delete_wire$169799 $delete_wire$171048 $delete_wire$169969 $delete_wire$170656 $delete_wire$169661 $delete_wire$171354 $delete_wire$170661 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
|
||||
connect \S $delete_wire$169671
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216097$6324_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169998 $delete_wire$171350 $delete_wire$170759 $delete_wire$169716 $delete_wire$169993 $delete_wire$169683 $delete_wire$170654 $delete_wire$169667 $delete_wire$170001 $delete_wire$171371 $delete_wire$169674 $delete_wire$170667 $delete_wire$169782 $delete_wire$171187 $delete_wire$170878 $delete_wire$170766 $delete_wire$171254 $delete_wire$169796 $delete_wire$170877 $delete_wire$169734 $delete_wire$169746 $delete_wire$171207 $delete_wire$169769 $delete_wire$170009 $delete_wire$169798 $delete_wire$171172 $delete_wire$169968 $delete_wire$171271 $delete_wire$169660 $delete_wire$171232 $delete_wire$170662 \dcsr_q_prv__0_ }
|
||||
connect \B $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
|
||||
connect \S $delete_wire$169831
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216098$6323_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$169811 $delete_wire$171355 $delete_wire$170763 $delete_wire$169715 $delete_wire$171039 $delete_wire$169682 $delete_wire$169988 $delete_wire$169657 $delete_wire$170015 $delete_wire$171317 $delete_wire$169673 $delete_wire$170866 $delete_wire$169768 $delete_wire$170998 $delete_wire$170752 $delete_wire$170023 $delete_wire$170767 $delete_wire$169795 $delete_wire$170030 $delete_wire$169733 $delete_wire$169745 $delete_wire$171360 $delete_wire$169834 $delete_wire$170010 $delete_wire$169976 $delete_wire$171203 $delete_wire$169967 $delete_wire$171477 $delete_wire$169659 $delete_wire$171230 $delete_wire$170641 \dcsr_q_prv__0_ }
|
||||
connect \B $delete_wire$169713
|
||||
connect \S $delete_wire$171001
|
||||
connect \Y $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:216099$6322_Y
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:217099$7332
|
||||
parameter \WIDTH 32
|
||||
connect \A { $delete_wire$170013 $delete_wire$171353 $delete_wire$171037 $delete_wire$169714 $delete_wire$171269 $delete_wire$169681 $delete_wire$170668 $delete_wire$169656 $delete_wire$170003 $delete_wire$171189 $delete_wire$169672 $delete_wire$169960 $delete_wire$169780 $delete_wire$170775 $delete_wire$170871 $delete_wire$170864 $delete_wire$171183 $delete_wire$169808 $delete_wire$170017 $delete_wire$169732 $delete_wire$169744 $delete_wire$171359 $delete_wire$171041 $delete_wire$171040 $delete_wire$170761 $delete_wire$170635 $delete_wire$169966 $delete_wire$169971 $delete_wire$169701 $delete_wire$170648 $delete_wire$171255 \dcsr_q_prv__0_ }
|
||||
connect \B { $delete_wire$169829 $delete_wire$171316 $delete_wire$169836 $delete_wire$169678 $delete_wire$169676 $delete_wire$169766 $delete_wire$169827 $delete_wire$170039 $delete_wire$169703 $delete_wire$169652 $delete_wire$169706 $delete_wire$169708 $delete_wire$169987 $delete_wire$169711 $delete_wire$169985 $delete_wire$169758 $delete_wire$169973 $delete_wire$170011 $delete_wire$170869 $delete_wire$169812 $delete_wire$169964 $delete_wire$169824 $delete_wire$169654 $delete_wire$169838 $delete_wire$170035 $delete_wire$169840 $delete_wire$171341 $delete_wire$169832 $delete_wire$169761 $delete_wire$169797 $delete_wire$169763 \N2231 }
|
||||
connect \S $delete_wire$169760
|
||||
connect \Y { \dcsr_d [31:9] $delete_wire$171047 $delete_wire$170040 $delete_wire$170750 \dcsr_d [5:2] $delete_wire$171227 \N3558 }
|
||||
end
|
||||
cell $mux $ternary$/workspace/OpenROAD-flow-scripts/flow/designs/src/ariane133/ariane.sv2v.v:217233$7498
|
||||
parameter \WIDTH 5
|
||||
connect \A { $delete_wire$169995 $delete_wire$169651 $delete_wire$171042 $delete_wire$171201 }
|
||||
connect \B { $delete_wire$170867 $delete_wire$170041 $delete_wire$171178 $delete_wire$171358 \N3558 }
|
||||
connect \S $delete_wire$170771
|
||||
connect \Y { \dcsr_d [8:6] \dcsr_d [1:0] }
|
||||
end
|
||||
end
|
||||
58
tests/opt/opt_dff-simplify.ys
Normal file
58
tests/opt/opt_dff-simplify.ys
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# 5279 issue
|
||||
# Check only for complimentary patterns elimination
|
||||
|
||||
read_rtlil opt_dff-simplify.il
|
||||
|
||||
select -assert-count 0 t:$adffe
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 0 t:$ne
|
||||
|
||||
opt_dff
|
||||
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 0 t:$adff
|
||||
|
||||
select -assert-count 8 t:$ne r:A_WIDTH=3 %i
|
||||
select -assert-count 5 t:$ne r:A_WIDTH=2 %i
|
||||
|
||||
select -assert-none t:$ne r:A_WIDTH=13 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=14 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=15 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=10 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=12 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=11 %i
|
||||
|
||||
# Check for both complimentary and redundancy elimination
|
||||
|
||||
read_verilog << EOT
|
||||
module test(input clk, input h, input i, input m, output reg p);
|
||||
wire D;
|
||||
wire a;
|
||||
wire j;
|
||||
wire c;
|
||||
wire mux_test;
|
||||
wire n;
|
||||
|
||||
always @(posedge clk)
|
||||
p <= D;
|
||||
assign j = n ? 1'hx : a;
|
||||
assign a = i ? mux_test : p;
|
||||
assign D = m ? h : j;
|
||||
assign c = n ? 1'hx : p;
|
||||
assign mux_test = m ? 1'hx : c;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
cd test
|
||||
proc
|
||||
|
||||
select -assert-count 0 t:$dffe
|
||||
select -assert-count 1 t:$dff
|
||||
select -assert-count 0 t:$ne
|
||||
|
||||
opt_dff
|
||||
|
||||
select -assert-count 1 t:$dffe
|
||||
select -assert-count 0 t:$dff
|
||||
select -assert-count 1 t:$ne r:A_WIDTH=2 %i
|
||||
select -assert-none t:$ne r:A_WIDTH=3 %i
|
||||
10
tests/verilog/sva-in-case-expr.ys
Normal file
10
tests/verilog/sva-in-case-expr.ys
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
read_verilog -sv <<EOT
|
||||
module test(input wire A);
|
||||
localparam TEST = 1;
|
||||
always_comb begin
|
||||
case (A)
|
||||
TEST: assert(1);
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
EOT
|
||||
Loading…
Add table
Add a link
Reference in a new issue