mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-15 22:21:30 +00:00
Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan
parent
c2291c10a6
commit
e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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@ -909,7 +909,7 @@ void AigerReader::post_process()
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module->rename(cell, escaped_s);
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}
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else
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log_error("Symbol type '%s' not recognised.\n", type.c_str());
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log_error("Symbol type '%s' not recognised.\n", type);
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}
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}
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@ -91,7 +91,7 @@ struct Xaiger2Frontend : public Frontend {
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std::ifstream map_file;
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map_file.open(map_filename);
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if (!map_file)
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log_error("Failed to open map file '%s'\n", map_filename.c_str());
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log_error("Failed to open map file '%s'\n", map_filename);
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unsigned int M, I, L, O, A;
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std::string header;
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@ -388,7 +388,7 @@ struct Xaiger2Frontend : public Frontend {
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if (f->eof())
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break;
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log_assert(!f->fail());
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log("input file: %s\n", scratch.c_str());
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log("input file: %s\n", scratch);
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}
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log_debug("co_counter=%d\n", co_counter);
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@ -1108,9 +1108,9 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
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log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
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if (defer)
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log("Storing AST representation for module `%s'.\n", ast->str.c_str());
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log("Storing AST representation for module `%s'.\n", ast->str);
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else if (!quiet) {
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log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
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log("Generating RTLIL representation for module `%s'.\n", ast->str);
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}
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AstModule *module = new AstModule;
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@ -1411,7 +1411,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
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for (auto& n : design->verilog_packages) {
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for (auto &o : n->children) {
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auto cloned_node = o->clone();
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// log("cloned node %s\n", type2str(cloned_node->type).c_str());
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// log("cloned node %s\n", type2str(cloned_node->type));
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if (cloned_node->type == AST_ENUM) {
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for (auto &e : cloned_node->children) {
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log_assert(e->type == AST_ENUM_ITEM);
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@ -1432,7 +1432,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
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for (const auto& node : child->children)
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if (node->type == AST_PARAMETER && param_has_no_default(node.get()))
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{
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log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
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log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str);
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defer_local = true;
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break;
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}
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@ -1507,7 +1507,7 @@ std::pair<std::string,std::string> AST::split_modport_from_type(std::string name
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interface_modport = seglist[1];
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}
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else { // Erroneous port type
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log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
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log_error("More than two '.' in signal port type (%s)\n", name_type);
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}
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}
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return std::pair<std::string,std::string>(interface_type, interface_modport);
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@ -1720,7 +1720,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
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new_subcell->set_bool_attribute(ID::is_interface);
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}
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else {
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log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
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log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
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}
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}
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@ -1731,7 +1731,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
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} else {
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modname = new_modname;
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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log("Found cached RTLIL representation for module `%s'.\n", modname);
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}
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return modname;
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@ -1750,7 +1750,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
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process_module(design, new_ast.get(), false, NULL, quiet);
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design->module(modname)->check();
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} else if (!quiet) {
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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log("Found cached RTLIL representation for module `%s'.\n", modname);
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}
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return modname;
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@ -1799,14 +1799,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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auto it = parameters.find(child->str);
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if (it != parameters.end()) {
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if (!quiet)
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
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log("Parameter %s = %s\n", child->str, log_signal(it->second));
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named_parameters.emplace_back(child->str, it->second);
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continue;
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}
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it = parameters.find(stringf("$%d", para_counter));
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if (it != parameters.end()) {
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if (!quiet)
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
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log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
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named_parameters.emplace_back(child->str, it->second);
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continue;
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}
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@ -1839,13 +1839,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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auto it = parameters.find(child->str);
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if (it != parameters.end()) {
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if (!quiet)
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
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log("Parameter %s = %s\n", child->str, log_signal(it->second));
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goto rewrite_parameter;
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}
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it = parameters.find(stringf("$%d", para_counter));
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if (it != parameters.end()) {
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if (!quiet)
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
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log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
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goto rewrite_parameter;
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}
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continue;
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@ -40,7 +40,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
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plugin_name = loaded_plugin_aliases.at(plugin_name);
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if (loaded_plugins.count(plugin_name) == 0)
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log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name.c_str(), plugin_name.c_str());
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log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name, plugin_name);
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void *symbol = dlsym(loaded_plugins.at(plugin_name), real_symbol_name.c_str());
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@ -61,7 +61,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
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if (symbol != nullptr)
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return (ffi_fptr) symbol;
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log_error("unable to resolve '%s'.\n", symbol_name.c_str());
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log_error("unable to resolve '%s'.\n", symbol_name);
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}
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std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<std::unique_ptr<AST::AstNode>> &args)
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@ -74,32 +74,32 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
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ffi_cif cif;
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int status;
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log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str());
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log("Calling DPI function `%s' and returning `%s':\n", fname, rtype);
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log_assert(GetSize(args) == GetSize(argtypes));
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for (int i = 0; i < GetSize(args); i++) {
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if (argtypes[i] == "real") {
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log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
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log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
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value_store[i].f64 = args[i]->asReal(args[i]->is_signed);
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values[i] = &value_store[i].f64;
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types[i] = &ffi_type_double;
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} else if (argtypes[i] == "shortreal") {
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log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
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log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
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value_store[i].f32 = args[i]->asReal(args[i]->is_signed);
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values[i] = &value_store[i].f32;
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types[i] = &ffi_type_double;
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} else if (argtypes[i] == "integer") {
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log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed));
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log(" arg %d (%s): %lld\n", i, argtypes[i], (long long)args[i]->asInt(args[i]->is_signed));
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value_store[i].i32 = args[i]->asInt(args[i]->is_signed);
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values[i] = &value_store[i].i32;
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types[i] = &ffi_type_sint32;
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} else if (argtypes[i] == "chandle") {
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log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false));
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log(" arg %d (%s): %llx\n", i, argtypes[i], (unsigned long long)args[i]->asInt(false));
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value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed);
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values[i] = &value_store[i].ptr;
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types[i] = &ffi_type_pointer;
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} else {
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log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i);
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log_error("invalid argtype '%s' for argument %d.\n", argtypes[i], i);
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}
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}
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@ -116,7 +116,7 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
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types[args.size()] = &ffi_type_pointer;
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values[args.size()] = &value_store[args.size()].ptr;
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} else {
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log_error("invalid rtype '%s'.\n", rtype.c_str());
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log_error("invalid rtype '%s'.\n", rtype);
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}
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if ((status = ffi_prep_cif(&cif, FFI_DEFAULT_ABI, args.size(), types[args.size()], types.data())) != FFI_OK)
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@ -155,7 +155,7 @@ YOSYS_NAMESPACE_BEGIN
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std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType, const std::string&, const std::string &fname, const std::vector<std::string>&, const std::vector<std::unique_ptr<AST::AstNode>>&)
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{
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log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str());
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log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname);
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}
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YOSYS_NAMESPACE_END
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@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator
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if (found_anyedge_syncs) {
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if (found_global_syncs)
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always->input_error("Found non-synthesizable event list!\n");
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log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str());
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log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string());
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log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
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log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
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}
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@ -180,10 +180,10 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
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if (template_node->attributes.count(ID::enum_type)) {
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//get reference to enum node:
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std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
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// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
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// log("enum_type=%s (count=%lu)\n", enum_type, current_scope.count(enum_type));
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// log("current scope:\n");
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// for (auto &it : current_scope)
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// log(" %s\n", it.first.c_str());
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// log(" %s\n", it.first);
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log_assert(current_scope.count(enum_type) == 1);
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AstNode *enum_node = current_scope.at(enum_type);
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log_assert(enum_node->type == AST_ENUM);
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@ -911,7 +911,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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#if 0
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log("-------------\n");
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log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this);
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log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename, location.begin.line, type2str(type), this);
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log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
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int(const_fold), int(stage), int(width_hint), int(sign_hint));
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// dumpAst(nullptr, "> ");
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@ -963,7 +963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
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goto verbose_activate;
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// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
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// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
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continue;
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verbose_activate:
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@ -978,7 +978,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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}
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silent_activate:
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// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
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// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
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mem2reg_set.insert(mem);
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}
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@ -1063,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
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if (str.substr(0, 8) == "$display")
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fmt.append_literal("\n");
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log("%s", fmt.render().c_str());
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log("%s", fmt.render());
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}
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return false;
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@ -1499,7 +1499,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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break;
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case AST_ENUM:
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//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
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//log("\nENUM %s: %d child %d\n", str, basic_prep, children[0]->basic_prep);
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if (!basic_prep) {
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for (auto& item_node : children) {
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while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
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@ -1590,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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}
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default:
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log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str());
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log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type));
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}
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}
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@ -2297,7 +2297,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
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str = try_pop_module_prefix();
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for (auto& node : current_scope_ast->children) {
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//log("looking at mod scope child %s\n", type2str(node->type).c_str());
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//log("looking at mod scope child %s\n", type2str(node->type));
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switch (node->type) {
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case AST_PARAMETER:
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case AST_LOCALPARAM:
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@ -2308,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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case AST_FUNCTION:
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case AST_TASK:
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case AST_DPI_FUNCTION:
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//log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str());
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//log("found child %s, %s\n", type2str(node->type), node->str);
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if (str == node->str) {
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//log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str());
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//log("add %s, type %s to scope\n", str, type2str(node->type));
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current_scope[node->str] = node.get();
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}
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break;
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@ -2319,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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for (auto& enum_node : node->children) {
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log_assert(enum_node->type==AST_ENUM_ITEM);
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if (str == enum_node->str) {
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//log("\nadding enum item %s to scope\n", str.c_str());
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//log("\nadding enum item %s to scope\n", str);
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current_scope[str] = enum_node.get();
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}
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}
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@ -5404,7 +5404,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
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#if 0
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log("-----------------------------------\n");
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for (auto &it : variables)
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log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val));
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log("%20s %40s\n", it.first, log_signal(it.second.val));
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stmt->dumpAst(nullptr, "stmt> ");
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#endif
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if (stmt->type == AST_WIRE)
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@ -618,7 +618,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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error:
|
||||
log_error("Syntax error in line %d!\n", line_count);
|
||||
error_with_reason:
|
||||
log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
|
||||
log_error("Syntax error in line %d: %s\n", line_count, err_reason);
|
||||
}
|
||||
|
||||
struct BlifFrontend : public Frontend {
|
||||
|
|
|
|||
|
|
@ -289,7 +289,7 @@ void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
|
|||
|
||||
void json_import(Design *design, string &modname, JsonNode *node)
|
||||
{
|
||||
log("Importing module %s from JSON tree.\n", modname.c_str());
|
||||
log("Importing module %s from JSON tree.\n", modname);
|
||||
|
||||
Module *module = new RTLIL::Module;
|
||||
module->name = RTLIL::escape_id(modname.c_str());
|
||||
|
|
@ -367,7 +367,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
|
|||
port_wire->port_input = true;
|
||||
port_wire->port_output = true;
|
||||
} else
|
||||
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str());
|
||||
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string);
|
||||
|
||||
port_wire->port_id = port_id;
|
||||
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
|
|||
|
||||
std::string id = RTLIL::escape_id(std::string(expr, id_len));
|
||||
if (!module->wires_.count(id))
|
||||
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
|
||||
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id));
|
||||
|
||||
expr += id_len;
|
||||
return module->wires_.at(id);
|
||||
|
|
@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend {
|
|||
if (cell->id != "cell" || cell->args.size() != 1)
|
||||
continue;
|
||||
|
||||
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
|
||||
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name));
|
||||
|
||||
std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
|
||||
parse_type_map(type_map, cell);
|
||||
|
|
@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend {
|
|||
{
|
||||
if (!flag_ignore_miss_dir)
|
||||
{
|
||||
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
|
||||
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name));
|
||||
} else {
|
||||
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
|
||||
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0));
|
||||
delete module;
|
||||
goto skip_cell;
|
||||
}
|
||||
|
|
@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend {
|
|||
if (node->id == "bus" && node->args.size() == 1)
|
||||
{
|
||||
if (flag_ignore_buses) {
|
||||
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
|
||||
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0));
|
||||
delete module;
|
||||
goto skip_cell;
|
||||
}
|
||||
|
|
@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
|
|||
}
|
||||
|
||||
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
|
||||
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
|
||||
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name));
|
||||
|
||||
simple_comb_cell = false;
|
||||
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ struct RpcModule : RTLIL::Module {
|
|||
|
||||
std::string parameter_info;
|
||||
for (auto ¶m : parameters) {
|
||||
log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second)));
|
||||
log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second)));
|
||||
parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second)));
|
||||
}
|
||||
|
||||
|
|
@ -180,7 +180,7 @@ struct RpcModule : RTLIL::Module {
|
|||
derived_name = "$paramod" + stripped_name + parameter_info;
|
||||
|
||||
if (design->has(derived_name)) {
|
||||
log("Found cached RTLIL representation for module `%s'.\n", derived_name.c_str());
|
||||
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
|
||||
} else {
|
||||
std::string command, input;
|
||||
std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters);
|
||||
|
|
@ -437,7 +437,7 @@ struct RpcFrontend : public Pass {
|
|||
|
||||
command_path_len_w = SearchPathW(/*lpPath=*/NULL, /*lpFileName=*/command_w.c_str(), /*lpExtension=*/L".exe", /*nBufferLength=*/0, /*lpBuffer=*/NULL, /*lpFilePart=*/NULL);
|
||||
if (command_path_len_w == 0) {
|
||||
log_error("SearchPathW failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("SearchPathW failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
command_path_w.resize(command_path_len_w - 1);
|
||||
|
|
@ -448,19 +448,19 @@ struct RpcFrontend : public Pass {
|
|||
pipe_attr.bInheritHandle = TRUE;
|
||||
pipe_attr.lpSecurityDescriptor = NULL;
|
||||
if (!CreatePipe(&send_r, &send_w, &pipe_attr, /*nSize=*/0)) {
|
||||
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("CreatePipe failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
if (!SetHandleInformation(send_w, HANDLE_FLAG_INHERIT, 0)) {
|
||||
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
if (!CreatePipe(&recv_r, &recv_w, &pipe_attr, /*nSize=*/0)) {
|
||||
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("CreatePipe failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
if (!SetHandleInformation(recv_r, HANDLE_FLAG_INHERIT, 0)) {
|
||||
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
|
||||
|
|
@ -470,7 +470,7 @@ struct RpcFrontend : public Pass {
|
|||
startup_info.hStdError = GetStdHandle(STD_ERROR_HANDLE);
|
||||
startup_info.dwFlags |= STARTF_USESTDHANDLES;
|
||||
if (!CreateProcessW(/*lpApplicationName=*/command_path_w.c_str(), /*lpCommandLine=*/&command_line_w[0], /*lpProcessAttributes=*/NULL, /*lpThreadAttributes=*/NULL, /*bInheritHandles=*/TRUE, /*dwCreationFlags=*/0, /*lpEnvironment=*/NULL, /*lpCurrentDirectory=*/NULL, &startup_info, &proc_info)) {
|
||||
log_error("CreateProcessW failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("CreateProcessW failed: %s\n", get_last_error_str());
|
||||
goto cleanup_exec;
|
||||
}
|
||||
CloseHandle(proc_info.hProcess);
|
||||
|
|
@ -550,7 +550,7 @@ cleanup_exec:
|
|||
|
||||
h = CreateFileW(path_w.c_str(), GENERIC_READ|GENERIC_WRITE, /*dwShareMode=*/0, /*lpSecurityAttributes=*/NULL, /*dwCreationDisposition=*/OPEN_EXISTING, /*dwFlagsAndAttributes=*/0, /*hTemplateFile=*/NULL);
|
||||
if (h == INVALID_HANDLE_VALUE) {
|
||||
log_error("CreateFileW failed: %s\n", get_last_error_str().c_str());
|
||||
log_error("CreateFileW failed: %s\n", get_last_error_str());
|
||||
goto cleanup_path;
|
||||
}
|
||||
|
||||
|
|
@ -586,7 +586,7 @@ cleanup_path:
|
|||
log_cmd_error("Failed to connect to RPC frontend.\n");
|
||||
|
||||
for (auto &module_name : server->get_module_names()) {
|
||||
log("Linking module `%s'.\n", module_name.c_str());
|
||||
log("Linking module `%s'.\n", module_name);
|
||||
RpcModule *module = new RpcModule;
|
||||
module->name = "$abstract\\" + module_name;
|
||||
module->server = server;
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ struct RTLILFrontend : public Frontend {
|
|||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
log("Input filename: %s\n", filename.c_str());
|
||||
log("Input filename: %s\n", filename);
|
||||
|
||||
RTLIL_FRONTEND::lexin = f;
|
||||
RTLIL_FRONTEND::current_design = design;
|
||||
|
|
|
|||
|
|
@ -143,7 +143,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
|
|||
if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
|
||||
log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
|
||||
else
|
||||
log("%s%s\n", message_prefix.c_str(), message.c_str());
|
||||
log("%s%s\n", message_prefix, message);
|
||||
}
|
||||
if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR))
|
||||
verific_error_msg = message;
|
||||
|
|
@ -250,7 +250,7 @@ static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
|
|||
{
|
||||
if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
|
||||
return RTLIL::Const::from_string(val.substr(1,val.size()-2));
|
||||
log_error("Error parsing VHDL %s.\n", typ.c_str());
|
||||
log_error("Error parsing VHDL %s.\n", typ);
|
||||
}
|
||||
|
||||
static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
|
||||
|
|
@ -261,7 +261,7 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string
|
|||
c.flags |= RTLIL::CONST_FLAG_SIGNED;
|
||||
return c;
|
||||
}
|
||||
log_error("Error parsing VHDL %s.\n", typ.c_str());
|
||||
log_error("Error parsing VHDL %s.\n", typ);
|
||||
}
|
||||
|
||||
static const RTLIL::Const extract_vhdl_integer(std::string &val)
|
||||
|
|
@ -2655,7 +2655,7 @@ struct VerificExtNets
|
|||
cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
|
||||
}
|
||||
|
||||
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str());
|
||||
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A), get_full_netlist_name(B));
|
||||
}
|
||||
|
||||
void run(Netlist *nl)
|
||||
|
|
@ -2679,17 +2679,17 @@ struct VerificExtNets
|
|||
continue;
|
||||
|
||||
if (verific_verbose)
|
||||
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name());
|
||||
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl), inst->Name(), port->Name());
|
||||
|
||||
Netlist *ext_nl = net->Owner();
|
||||
|
||||
if (verific_verbose)
|
||||
log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str());
|
||||
log(" external net owner: %s\n", get_full_netlist_name(ext_nl));
|
||||
|
||||
Netlist *ca_nl = find_common_ancestor(nl, ext_nl);
|
||||
|
||||
if (verific_verbose)
|
||||
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str());
|
||||
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl));
|
||||
|
||||
Net *ca_net = route_up(net, !port->IsOutput(), ca_nl);
|
||||
Net *new_net = ca_net;
|
||||
|
|
@ -3038,7 +3038,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
|
|||
}
|
||||
|
||||
if (!verific_error_msg.empty())
|
||||
log_error("%s\n", verific_error_msg.c_str());
|
||||
log_error("%s\n", verific_error_msg);
|
||||
|
||||
for (auto nl : nl_todo)
|
||||
nl.second->ChangePortBusStructures(1 /* hierarchical */);
|
||||
|
|
@ -3060,7 +3060,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
|
|||
|
||||
verific_cleanup();
|
||||
if (!verific_error_msg.empty())
|
||||
log_error("%s\n", verific_error_msg.c_str());
|
||||
log_error("%s\n", verific_error_msg);
|
||||
return top;
|
||||
}
|
||||
|
||||
|
|
@ -3349,7 +3349,7 @@ struct VerificPass : public Pass {
|
|||
char block[4096];
|
||||
while (1) {
|
||||
if (fgets(block, 4096, Frontend::current_script_file == nullptr? stdin : Frontend::current_script_file) == nullptr)
|
||||
log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
|
||||
log_error("Unexpected end of file in here document '%s'!\n", filename);
|
||||
buffer += block;
|
||||
if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
|
||||
break;
|
||||
|
|
@ -4232,7 +4232,7 @@ struct VerificPass : public Pass {
|
|||
}
|
||||
lines.sort();
|
||||
for (auto &line : lines)
|
||||
log("verific -cfg %s\n", line.c_str());
|
||||
log("verific -cfg %s\n", line);
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
|
|
@ -4291,7 +4291,7 @@ struct VerificPass : public Pass {
|
|||
}
|
||||
|
||||
if (!verific_error_msg.empty())
|
||||
log_error("%s\n", verific_error_msg.c_str());
|
||||
log_error("%s\n", verific_error_msg);
|
||||
|
||||
}
|
||||
#else /* YOSYS_ENABLE_VERIFIC */
|
||||
|
|
|
|||
|
|
@ -1024,7 +1024,7 @@ struct VerificSvaImporter
|
|||
[[noreturn]] void parser_error(std::string errmsg)
|
||||
{
|
||||
if (!importer->mode_keep)
|
||||
log_error("%s", errmsg.c_str());
|
||||
log_error("%s", errmsg);
|
||||
log_warning("%s", errmsg.c_str());
|
||||
throw ParserErrorException();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ struct arg_map_t
|
|||
void add_arg(const std::string &name, const char *default_value)
|
||||
{
|
||||
if (find(name)) {
|
||||
log_error("Duplicate macro arguments with name `%s'.\n", name.c_str());
|
||||
log_error("Duplicate macro arguments with name `%s'.\n", name);
|
||||
}
|
||||
|
||||
name_to_pos[name] = args.size();
|
||||
|
|
@ -789,14 +789,14 @@ frontend_verilog_preproc(std::istream &f,
|
|||
else if (ifdef_pass_level > 0)
|
||||
ifdef_pass_level--;
|
||||
else
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`else") {
|
||||
if (ifdef_fail_level == 0) {
|
||||
if (ifdef_pass_level == 0)
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok);
|
||||
ifdef_pass_level--;
|
||||
ifdef_fail_level = 1;
|
||||
ifdef_already_satisfied = true;
|
||||
|
|
@ -813,7 +813,7 @@ frontend_verilog_preproc(std::istream &f,
|
|||
std::string name = next_token(true);
|
||||
if (ifdef_fail_level == 0) {
|
||||
if (ifdef_pass_level == 0)
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
|
||||
log_error("Found %s outside of macro conditional branch!\n", tok);
|
||||
ifdef_pass_level--;
|
||||
ifdef_fail_level = 1;
|
||||
ifdef_already_satisfied = true;
|
||||
|
|
|
|||
|
|
@ -497,7 +497,7 @@ struct VerilogFrontend : public Frontend {
|
|||
if (!flag_nopp) {
|
||||
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
|
||||
if (flag_ppdump)
|
||||
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
|
||||
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc);
|
||||
parse_state.lexin = new std::istringstream(code_after_preproc);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3261,7 +3261,7 @@ basic_expr:
|
|||
ConstParser p{@4};
|
||||
auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
|
||||
if (val == nullptr)
|
||||
log_error("Value conversion failed: `%s'\n", $4->c_str());
|
||||
log_error("Value conversion failed: `%s'\n", *$4);
|
||||
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move($2), std::move(val));
|
||||
} |
|
||||
hierarchical_id integral_number {
|
||||
|
|
@ -3274,7 +3274,7 @@ basic_expr:
|
|||
auto val = p.const2ast(*$2, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
|
||||
SET_AST_NODE_LOC(val.get(), @2, @2);
|
||||
if (val == nullptr)
|
||||
log_error("Value conversion failed: `%s'\n", $2->c_str());
|
||||
log_error("Value conversion failed: `%s'\n", *$2);
|
||||
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move(bits), std::move(val));
|
||||
} |
|
||||
integral_number {
|
||||
|
|
@ -3282,7 +3282,7 @@ basic_expr:
|
|||
$$ = p.const2ast(*$1, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
|
||||
SET_AST_NODE_LOC($$.get(), @1, @1);
|
||||
if ($$ == nullptr)
|
||||
log_error("Value conversion failed: `%s'\n", $1->c_str());
|
||||
log_error("Value conversion failed: `%s'\n", *$1);
|
||||
} |
|
||||
TOK_REALVAL {
|
||||
$$ = std::make_unique<AstNode>(@$, AST_REALVALUE);
|
||||
|
|
|
|||
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Add table
Add a link
Reference in a new issue