mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 10:05:33 +00:00
Code Activity
4981 commits 98 branches 53 tags 45 MiB
Commit graph

710 commits

Author SHA1 Message Date
David Shah
777864d02e ecp5: Demote conflicting FF init values to a warning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8 Fix ECP5 cells_sim for iverilog 2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode 
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
 2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 
EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
 2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve 
ECP5 Improvements
 2019-02-28 14:46:56 -08:00
Eddie Hung
1da0909662 Remove SRL16/32 from cells_xtra 2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960 Add SRL16 and SRL32 sim models 2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6 Fix SRL16/32 techmap off-by-one 2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de synth_xilinx to call shregmap with enable support 2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0 synth_xilinx to use shregmap with -params too 2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a synth_xilinx to now have shregmap call after dff2dffe 2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048 Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 2019-02-28 09:31:24 -08:00
Larry Doolittle
7a40294e93 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa ecp5: Compatibility with Migen AsyncResetSynchronizer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress 
Improve ABC netname preservation
 2019-02-22 01:16:34 +01:00
Clifford Wolf
2fe1c830eb Bugfix in ice40_dsp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:28:46 +01:00
Clifford Wolf
84999a7e68 Add ice40 test_dsp_map test case generator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185 Improve iCE40 SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 12:55:20 +01:00
David Shah
bb56cb738d ecp5: Add DDRDLLA 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-19 19:34:37 +00:00
David Shah
c36f15b489 ecp5: Add DELAYF/DELAYG blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2 Add first draft of functional SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-19 14:47:27 +01:00
David Shah
e0bc190879 ecp5: Add ECLKSYNCB blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-13 11:23:25 +00:00
David Shah
7913baedd8 ecp5: Full set of IO-related blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 12:04:41 +00:00
David Shah
95789c6136 ecp5: Use abc -dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah
7ef2333497 ice40: Use abc -dress in synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2 ecp5: Support for flipflop initialisation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f ecp5: Add LSRMODE to flipflops for PRLD support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1 ecp5: More blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:34:34 +00:00
David Shah
01ea72f53a ecp5: Increase threshold for ALU mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:33:47 +00:00
Clifford Wolf
db5765b443 Add SF2 IO buffer insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 14:38:37 +01:00
Clifford Wolf
841ca74c90 Add "synth_sf2 -vlog", fix "synth_sf2 -edif" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:33:45 +01:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix 
Fix cells_sim.v for Achronix FPGA
 2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4 Fix cells_sim.v for Achronix FPGA 2019-01-04 15:15:23 +01:00
Miodrag Milanovic
3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
Clifford Wolf
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init 
anlogic: implement DRAM initialization
 2019-01-02 16:28:18 +01:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init 
Initialization of Anlogic DFFs
 2019-01-02 15:52:22 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut 
cmp2lut: new techmap pass
 2019-01-02 15:43:10 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark
17b2831356 synth_ice40: use 4-LUT coarse synthesis mode. 2019-01-02 08:25:55 +00:00
whitequark
18174202a9 synth: add k-LUT mode. 2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73 synth: improve script documentation. NFC. 2019-01-02 08:05:44 +00:00