Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.

techlibs/achronix/speedster22i/cells_map.v

@@ -32,7 +32,7 @@ endmodule
 // > end buffers <
 
 // > Look-Up table <
-// > VT: I still think Achronix folks would have choosen a better \
+// > VT: I still think Achronix folks would have chosen a better \
 // >     logic architecture.
 // LUT Map
 module \$lut (A, Y);
@@ -43,30 +43,30 @@ module \$lut (A, Y);
    generate
       if (WIDTH == 1) begin
 	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
-         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
            (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
       end else
       if (WIDTH == 2) begin
-              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
       end else
       if(WIDTH == 3) begin
-	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ 
+	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
       end else
       if(WIDTH == 4) begin
-             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ 
+             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
       end else
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
-endmodule 
+endmodule
 // > end LUT <
 
 // > Flops <
 // DFF flop
 module  \$_DFF_P_ (input D, C, output Q);
-   DFF _TECHMAP_REPLACE_ 
+   DFF _TECHMAP_REPLACE_
      (.q(Q), .d(D), .ck(C));
-endmodule 
+endmodule
 

techlibs/achronix/synth_achronix.cc

@@ -108,7 +108,7 @@ struct SynthAchronixPass : public ScriptPass {
     extra_args(args, argidx, design);
 
     if (!design->full_selection())
-      log_cmd_error("This comannd only operates on fully selected designs!\n");
+      log_cmd_error("This command only operates on fully selected designs!\n");
 
     log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
     log_push();

techlibs/anlogic/synth_anlogic.cc

@@ -119,7 +119,7 @@ struct SynthAnlogicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ANLOGIC pass.\n");
 		log_push();

techlibs/common/prep.cc

@@ -153,7 +153,7 @@ struct PrepPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing PREP pass.\n");
 		log_push();

techlibs/common/synth.cc

@@ -155,7 +155,7 @@ struct SynthPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH pass.\n");
 		log_push();

techlibs/coolrunner2/synth_coolrunner2.cc

@@ -111,7 +111,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
 		log_push();

techlibs/easic/synth_easic.cc

@@ -117,7 +117,7 @@ struct SynthEasicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_EASIC pass.\n");
 		log_push();

techlibs/ecp5/cells_bb.v

@@ -484,7 +484,7 @@ module DCUA(
 	parameter D_XGE_MODE = "0b0";
 
 // These parameters don't do anything but are
-// needed for compatability with Diamond
+// needed for compatibility with Diamond
 	parameter D_TX_MAX_RATE = "2.5";
 	parameter D_RX_MAX_RATE = "2.5";
 	parameter CH0_TXAMPLITUDE = "0d1300";

techlibs/ecp5/synth_ecp5.cc

@@ -189,7 +189,7 @@ struct SynthEcp5Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();

techlibs/gowin/synth_gowin.cc

@@ -109,7 +109,7 @@ struct SynthGowinPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_GOWIN pass.\n");
 		log_push();

techlibs/greenpak4/synth_greenpak4.cc

@@ -120,7 +120,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 			log_cmd_error("Invalid part name: '%s'\n", part.c_str());

techlibs/ice40/synth_ice40.cc

@@ -198,7 +198,7 @@ struct SynthIce40Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();

techlibs/intel/cyclonev/cells_sim.v

@@ -54,7 +54,7 @@ module cyclonev_lcell_comb
    // Internal variables
    // Sub mask for fragmented LUTs
    wire [15:0] mask_a, mask_b, mask_c, mask_d;
-   // Independant output for fragmented LUTs
+   // Independent output for fragmented LUTs
    wire        output_0, output_1, output_2, output_3;
    // Extended mode uses mux to define the output
    wire        mux_0, mux_1;

techlibs/sf2/synth_sf2.cc

@@ -118,7 +118,7 @@ struct SynthSf2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_SF2 pass.\n");
 		log_push();

techlibs/xilinx/synth_xilinx.cc

@@ -178,7 +178,7 @@ struct SynthXilinxPass : public Pass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		bool active = run_from.empty();