3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00

Fixed Anlogic simulation model

This commit is contained in:
Miodrag Milanovic 2019-01-25 19:25:25 +01:00
parent c4b61f2d69
commit 0de328da8f

View file

@ -17,7 +17,7 @@ module AL_MAP_LUT1 (
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign Y = INIT >> A;
assign o = INIT >> a;
endmodule
module AL_MAP_LUT2 (