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Clean up some whitepsace outliers

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Larry Doolittle 2019-02-24 22:08:52 -08:00 • committed by Clifford Wolf
parent c258b99040
commit 61fc411c5d
3 changed files with 6 additions and 6 deletions
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4
techlibs/ecp5/cells_sim.v
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@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1
);
parameter WCKMUX = "WCK";
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000;
@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;