mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

synth_xilinx to now have shregmap call after dff2dffe

Browse source
This commit is contained in:
Eddie Hung 2019-02-28 09:32:29 -08:00
parent c29f0c5048
commit c9ab18889a
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -103,6 +103,7 @@ struct SynthXilinxPass : public Pass
log(" memory_map\n");
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" shregmap -init\n");
log(" opt -full\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" opt -fast\n");
@ -222,6 +223,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "memory_map");
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
Pass::call(design, "shregmap -init");
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
Pass::call(design, "opt -fast");