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Add first draft of functional SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
5a853ed46c
commit
62493c91b2
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@ -886,59 +886,6 @@ module SB_WARMBOOT (
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);
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endmodule
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// UltraPlus feature cells
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(* blackbox *)
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module SB_MAC16 (
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input CLK,
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input CE,
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input [15:0] C,
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input [15:0] A,
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input [15:0] B,
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input [15:0] D,
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input AHOLD,
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input BHOLD,
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input CHOLD,
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input DHOLD,
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input IRSTTOP,
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input IRSTBOT,
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input ORSTTOP,
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input ORSTBOT,
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input OLOADTOP,
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input OLOADBOT,
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input ADDSUBTOP,
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input ADDSUBBOT,
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input OHOLDTOP,
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input OHOLDBOT,
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input CI,
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input ACCUMCI,
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input SIGNEXTIN,
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output [31:0] O,
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output CO,
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output ACCUMCO,
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output SIGNEXTOUT
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);
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parameter NEG_TRIGGER = 1'b0;
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parameter C_REG = 1'b0;
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parameter A_REG = 1'b0;
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parameter B_REG = 1'b0;
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parameter D_REG = 1'b0;
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parameter TOP_8x8_MULT_REG = 1'b0;
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parameter BOT_8x8_MULT_REG = 1'b0;
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parameter PIPELINE_16x16_MULT_REG1 = 1'b0;
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parameter PIPELINE_16x16_MULT_REG2 = 1'b0;
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parameter TOPOUTPUT_SELECT = 2'b00;
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parameter TOPADDSUB_LOWERINPUT = 2'b00;
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parameter TOPADDSUB_UPPERINPUT = 1'b0;
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parameter TOPADDSUB_CARRYSELECT = 2'b00;
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parameter BOTOUTPUT_SELECT = 2'b00;
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parameter BOTADDSUB_LOWERINPUT = 2'b00;
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parameter BOTADDSUB_UPPERINPUT = 1'b0;
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parameter BOTADDSUB_CARRYSELECT = 2'b00;
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parameter MODE_8x8 = 1'b0;
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parameter A_SIGNED = 1'b0;
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parameter B_SIGNED = 1'b0;
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endmodule
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module SB_SPRAM256KA (
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input [13:0] ADDRESS,
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input [15:0] DATAIN,
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@ -1273,3 +1220,178 @@ module SB_IO_OD (
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endgenerate
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`endif
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endmodule
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module SB_MAC16 (
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input CLK, CE,
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input [15:0] C, A, B, D,
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input AHOLD, BHOLD, CHOLD, DHOLD,
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input IRSTTOP, IRSTBOT,
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input ORSTTOP, ORSTBOT,
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input OLOADTOP, OLOADBOT,
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input ADDSUBTOP, ADDSUBBOT,
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input OHOLDTOP, OHOLDBOT,
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input CI, ACCUMCI, SIGNEXTIN,
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output [31:0] O,
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output CO, ACCUMCO, SIGNEXTOUT
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);
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parameter [0:0] NEG_TRIGGER = 0;
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parameter [0:0] C_REG = 0;
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parameter [0:0] A_REG = 0;
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parameter [0:0] B_REG = 0;
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parameter [0:0] D_REG = 0;
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parameter [0:0] TOP_8x8_MULT_REG = 0;
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parameter [0:0] BOT_8x8_MULT_REG = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
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parameter [1:0] TOPOUTPUT_SELECT = 0;
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parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
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parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
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parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
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parameter [1:0] BOTOUTPUT_SELECT = 0;
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parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
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parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
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parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
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parameter [0:0] MODE_8x8 = 0;
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parameter [0:0] A_SIGNED = 0;
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parameter [0:0] B_SIGNED = 0;
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wire clock = CLK ^ NEG_TRIGGER;
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// internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
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// http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
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// https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
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wire [15:0] iA, iB, iC, iD;
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wire [15:0] iF, iJ, iK, iG;
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wire [31:0] iL, iH;
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wire [15:0] iW, iX, iP, iQ;
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wire [15:0] iY, iZ, iR, iS;
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wire HCI, LCI, LCO;
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// Regs C and A
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reg [15:0] rC, rA;
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always @(posedge clock, posedge IRSTTOP) begin
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if (IRSTTOP) begin
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rC <= 0;
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rA <= 0;
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end else if (CE) begin
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if (!CHOLD) rC <= C;
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if (!AHOLD) rA <= A;
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end
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end
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assign iC = C_REG ? rC : C;
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assign iA = A_REG ? rA : A;
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// Regs B and D
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reg [15:0] rB, rD;
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always @(posedge clock, posedge IRSTTOP) begin
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if (IRSTBOT) begin
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rB <= 0;
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rD <= 0;
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end else if (CE) begin
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if (!BHOLD) rB <= B;
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if (!DHOLD) rD <= D;
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end
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end
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assign iB = B_REG ? rB : B;
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assign iD = D_REG ? rD : D;
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// Multiplier Stage
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wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
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wire [15:0] Ah, Al, Bh, Bl;
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assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
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assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
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assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
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assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
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assign p_Ah_Bh = Ah * Bh;
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assign p_Al_Bh = Al * Bh;
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assign p_Ah_Bl = Ah * Bl;
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assign p_Al_Bl = Al * Bl;
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// Regs F and J
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reg [15:0] rF, rJ;
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always @(posedge clock, posedge IRSTTOP) begin
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if (IRSTTOP) begin
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rF <= 0;
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rJ <= 0;
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end else if (CE) begin
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rF <= p_Ah_Bh;
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if (!MODE_8x8) rJ <= p_Al_Bh;
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end
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end
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assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
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assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
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// Regs K and G
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reg [15:0] rK, rG;
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always @(posedge clock, posedge IRSTBOT) begin
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if (IRSTBOT) begin
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rK <= 0;
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rG <= 0;
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end else if (CE) begin
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if (!MODE_8x8) rK <= p_Ah_Bl;
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rG <= p_Al_Bl;
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end
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end
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assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
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assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
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// Adder Stage
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reg [31:0] P;
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always @* begin
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P = iG[7:0];
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P = P + (iG[15:8] + iK[7:0]) << 8;
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P = P + (iK[15:8] + iJ[7:0]) << 16;
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P = P + (iJ[15:8] + iF[7:0]) << 24;
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end
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assign iL = P;
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// Reg H
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reg [15:0] rH;
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always @(posedge clock, posedge IRSTBOT) begin
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if (IRSTBOT) begin
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rH <= 0;
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end else if (CE) begin
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if (!MODE_8x8) rH <= iL;
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end
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end
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assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
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// Hi Output Stage
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wire [15:0] XW, Oh;
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reg [15:0] rQ;
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assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
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assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
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assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
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assign CO = ACCUMCO ^ ADDSUBTOP;
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assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
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always @(posedge clock, posedge ORSTTOP) begin
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if (ORSTTOP) begin
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rQ <= 0;
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end else if (CE) begin
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if (!OHOLDTOP) rQ <= iP;
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end
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end
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assign iQ = rQ;
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assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
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assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
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assign SIGNEXTOUT = iX[15];
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// Lo Output Stage
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wire [15:0] YZ, Ol;
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reg [15:0] rS;
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assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
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assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
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assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
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assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
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always @(posedge clock, posedge ORSTBOT) begin
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if (ORSTBOT) begin
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rS <= 0;
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end else if (CE) begin
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if (!OHOLDTOP) rS <= iR;
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end
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end
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assign iS = rS;
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assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
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assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
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assign O = {Oh, Ol};
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endmodule
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87
techlibs/ice40/tests/test_dsp_model.gtkw
Normal file
87
techlibs/ice40/tests/test_dsp_model.gtkw
Normal file
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@ -0,0 +1,87 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Tue Feb 19 13:33:31 2019
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[*]
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[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
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[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
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[dumpfile_size] 119605
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[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
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[timestart] 0
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[size] 1850 1362
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[pos] 1816 32
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*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 223
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[signals_width] 142
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[sst_expanded] 1
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[sst_vpaned_height] 420
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@28
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testbench.CLK
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testbench.CE
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@200
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-
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@28
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testbench.REF_ACCUMCO
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testbench.UUT_ACCUMCO
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@200
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-
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@28
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testbench.REF_CO
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testbench.UUT_CO
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@200
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-
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@22
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testbench.REF_O[31:0]
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testbench.UUT_O[31:0]
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@200
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-
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@28
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testbench.REF_SIGNEXTOUT
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testbench.UUT_SIGNEXTOUT
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@200
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-
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@22
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testbench.A[15:0]
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testbench.B[15:0]
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testbench.C[15:0]
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testbench.D[15:0]
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@200
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-
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@28
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testbench.AHOLD
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testbench.BHOLD
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testbench.CHOLD
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testbench.DHOLD
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@200
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-
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@28
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testbench.SIGNEXTIN
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testbench.ACCUMCI
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testbench.CI
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@200
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-
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@28
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testbench.ADDSUBTOP
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testbench.ADDSUBBOT
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@200
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-
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@28
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testbench.IRSTTOP
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testbench.IRSTBOT
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@200
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-
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@29
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testbench.OHOLDTOP
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@28
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testbench.OHOLDBOT
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@200
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-
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@28
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testbench.OLOADTOP
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testbench.OLOADBOT
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@200
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-
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@28
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testbench.ORSTTOP
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testbench.ORSTBOT
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[pattern_trace] 1
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[pattern_trace] 0
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6
techlibs/ice40/tests/test_dsp_model.sh
Normal file
6
techlibs/ice40/tests/test_dsp_model.sh
Normal file
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@ -0,0 +1,6 @@
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#!/bin/bash
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set -ex
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sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
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iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
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./test_dsp_model
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199
techlibs/ice40/tests/test_dsp_model.v
Normal file
199
techlibs/ice40/tests/test_dsp_model.v
Normal file
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@ -0,0 +1,199 @@
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`timescale 1ns / 1ps
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module testbench;
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parameter [0:0] NEG_TRIGGER = 0;
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parameter [0:0] C_REG = 0;
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parameter [0:0] A_REG = 0;
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parameter [0:0] B_REG = 0;
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parameter [0:0] D_REG = 0;
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parameter [0:0] TOP_8x8_MULT_REG = 0;
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parameter [0:0] BOT_8x8_MULT_REG = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
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parameter [1:0] TOPOUTPUT_SELECT = 0;
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parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
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parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
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parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
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parameter [1:0] BOTOUTPUT_SELECT = 0;
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parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
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parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
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parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
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parameter [0:0] MODE_8x8 = 0;
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parameter [0:0] A_SIGNED = 0;
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parameter [0:0] B_SIGNED = 0;
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reg CLK, CE;
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reg [15:0] C, A, B, D;
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reg AHOLD, BHOLD, CHOLD, DHOLD;
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reg IRSTTOP, IRSTBOT;
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reg ORSTTOP, ORSTBOT;
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reg OLOADTOP, OLOADBOT;
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reg ADDSUBTOP, ADDSUBBOT;
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reg OHOLDTOP, OHOLDBOT;
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reg CI, ACCUMCI, SIGNEXTIN;
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output [31:0] REF_O, UUT_O;
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output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
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output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
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integer errcount = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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if (REF_O !== UUT_O) begin
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$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
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errcount = errcount + 1;
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end
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if (REF_CO !== UUT_CO) begin
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$display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
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errcount = errcount + 1;
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end
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if (REF_ACCUMCO !== UUT_ACCUMCO) begin
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$display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
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errcount = errcount + 1;
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end
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if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
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$display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
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errcount = errcount + 1;
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end
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#3;
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end
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endtask
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initial begin
|
||||
$dumpfile("test_dsp_model.vcd");
|
||||
$dumpvars(0, testbench);
|
||||
|
||||
#5;
|
||||
CLK = NEG_TRIGGER;
|
||||
CE = 1;
|
||||
{C, A, B, D} = 0;
|
||||
{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
|
||||
{IRSTTOP, IRSTBOT} = 0;
|
||||
{ORSTTOP, ORSTBOT} = 0;
|
||||
{OLOADTOP, OLOADBOT} = 0;
|
||||
{ADDSUBTOP, ADDSUBBOT} = 0;
|
||||
{OHOLDTOP, OHOLDBOT} = 0;
|
||||
{CI, ACCUMCI, SIGNEXTIN} = 0;
|
||||
|
||||
// C = 10;
|
||||
// A = 15;
|
||||
// B = 22;
|
||||
// D = 27;
|
||||
|
||||
repeat (10) clkcycle;
|
||||
|
||||
if (errcount == 0) begin
|
||||
$display("All tests passed.");
|
||||
end else begin
|
||||
$display("Caught %1d errors.", errcount);
|
||||
end
|
||||
end
|
||||
|
||||
SB_MAC16 #(
|
||||
.NEG_TRIGGER (NEG_TRIGGER ),
|
||||
.C_REG (C_REG ),
|
||||
.A_REG (A_REG ),
|
||||
.B_REG (B_REG ),
|
||||
.D_REG (D_REG ),
|
||||
.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
|
||||
.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
|
||||
.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
|
||||
.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
|
||||
.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
|
||||
.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
|
||||
.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
|
||||
.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
|
||||
.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
|
||||
.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
|
||||
.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
|
||||
.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
|
||||
.MODE_8x8 (MODE_8x8 ),
|
||||
.A_SIGNED (A_SIGNED ),
|
||||
.B_SIGNED (B_SIGNED )
|
||||
) ref (
|
||||
.CLK (CLK ),
|
||||
.CE (CE ),
|
||||
.C (C ),
|
||||
.A (A ),
|
||||
.B (B ),
|
||||
.D (D ),
|
||||
.AHOLD (AHOLD ),
|
||||
.BHOLD (BHOLD ),
|
||||
.CHOLD (CHOLD ),
|
||||
.DHOLD (DHOLD ),
|
||||
.IRSTTOP (IRSTTOP ),
|
||||
.IRSTBOT (IRSTBOT ),
|
||||
.ORSTTOP (ORSTTOP ),
|
||||
.ORSTBOT (ORSTBOT ),
|
||||
.OLOADTOP (OLOADTOP ),
|
||||
.OLOADBOT (OLOADBOT ),
|
||||
.ADDSUBTOP (ADDSUBTOP ),
|
||||
.ADDSUBBOT (ADDSUBBOT ),
|
||||
.OHOLDTOP (OHOLDTOP ),
|
||||
.OHOLDBOT (OHOLDBOT ),
|
||||
.CI (CI ),
|
||||
.ACCUMCI (ACCUMCI ),
|
||||
.SIGNEXTIN (SIGNEXTIN ),
|
||||
.O (REF_O ),
|
||||
.CO (REF_CO ),
|
||||
.ACCUMCO (REF_ACCUMCO ),
|
||||
.SIGNEXTOUT (REF_SIGNEXTOUT)
|
||||
);
|
||||
|
||||
SB_MAC16_UUT #(
|
||||
.NEG_TRIGGER (NEG_TRIGGER ),
|
||||
.C_REG (C_REG ),
|
||||
.A_REG (A_REG ),
|
||||
.B_REG (B_REG ),
|
||||
.D_REG (D_REG ),
|
||||
.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
|
||||
.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
|
||||
.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
|
||||
.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
|
||||
.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
|
||||
.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
|
||||
.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
|
||||
.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
|
||||
.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
|
||||
.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
|
||||
.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
|
||||
.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
|
||||
.MODE_8x8 (MODE_8x8 ),
|
||||
.A_SIGNED (A_SIGNED ),
|
||||
.B_SIGNED (B_SIGNED )
|
||||
) uut (
|
||||
.CLK (CLK ),
|
||||
.CE (CE ),
|
||||
.C (C ),
|
||||
.A (A ),
|
||||
.B (B ),
|
||||
.D (D ),
|
||||
.AHOLD (AHOLD ),
|
||||
.BHOLD (BHOLD ),
|
||||
.CHOLD (CHOLD ),
|
||||
.DHOLD (DHOLD ),
|
||||
.IRSTTOP (IRSTTOP ),
|
||||
.IRSTBOT (IRSTBOT ),
|
||||
.ORSTTOP (ORSTTOP ),
|
||||
.ORSTBOT (ORSTBOT ),
|
||||
.OLOADTOP (OLOADTOP ),
|
||||
.OLOADBOT (OLOADBOT ),
|
||||
.ADDSUBTOP (ADDSUBTOP ),
|
||||
.ADDSUBBOT (ADDSUBBOT ),
|
||||
.OHOLDTOP (OHOLDTOP ),
|
||||
.OHOLDBOT (OHOLDBOT ),
|
||||
.CI (CI ),
|
||||
.ACCUMCI (ACCUMCI ),
|
||||
.SIGNEXTIN (SIGNEXTIN ),
|
||||
.O (UUT_O ),
|
||||
.CO (UUT_CO ),
|
||||
.ACCUMCO (UUT_ACCUMCO ),
|
||||
.SIGNEXTOUT (UUT_SIGNEXTOUT)
|
||||
);
|
||||
endmodule
|
||||
Loading…
Reference in a new issue