Robert O'Callahan
ab525643a7
Don't reset the hash when unpacking, instead clear the hash whenever bits are modified
2025-10-31 11:53:39 +00:00
Robert O'Callahan
a1f7d6c9bf
Use size() instead of direct access to width_ in many places
2025-10-31 11:53:39 +00:00
Robert O'Callahan
dbb8354996
Remove unnecessary pack() from SigSpec::extend_u0()
2025-10-31 11:53:39 +00:00
Robert O'Callahan
d314c47a55
Simplify SigSpec::as_bit()
2025-10-31 11:53:39 +00:00
Robert O'Callahan
be530bef73
Instead of using packing and hashing to compute SigSpec ordering and equality, just use the width and chunkwise comparisons
...
This avoids having to pack and compute hashes, and generally results in a
simpler ordering.
2025-10-31 11:53:39 +00:00
Robert O'Callahan
973e8a3928
Build a temporary SigChunk list in the iterator in the cases where that's needed
2025-10-31 11:53:39 +00:00
Robert O'Callahan
8c9dd3209a
Make SigSpec conversion to vector of SigChunk use chunks iterator
2025-10-31 11:53:39 +00:00
Robert O'Callahan
4672127610
Make SigSpec::parse_rhs use is_chunk to avoid direct access to chunks_
2025-10-31 11:53:39 +00:00
Robert O'Callahan
11a91af920
Make SigSpec::to_sigbit_pool use chunk iterator
2025-10-31 11:53:39 +00:00
Robert O'Callahan
8cb7cd7ac1
Make SigSpec::to_sigbit_set use chunk iterator
2025-10-31 11:53:39 +00:00
Robert O'Callahan
82f86164d3
Use SigSpec::try_as_const in some places
2025-10-31 11:53:39 +00:00
Robert O'Callahan
0d45d9cc6e
Make SigSpec::is_one_hot use try_as_const
2025-10-31 11:53:39 +00:00
Robert O'Callahan
a0e9e2d364
Fix try_as_const/as_wire/as_chunk
2025-10-31 11:53:39 +00:00
Robert O'Callahan
000c081965
Add try_as_const and use the const iterator a bit more
2025-10-31 11:53:38 +00:00
Robert O'Callahan
04a6dbc562
Make SigSpec::has_marked_bits use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
7bd6b4f287
Make SigSpec::has_const(State) use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
213d665ae1
Make SigSpec::has_const use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
5c8f9f14ca
Make SigSpec::is_fully_undef use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
b2de56cae2
Make SigSpec::is_fully_def use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
8a88acd9b8
Make SigSpec::is_fully_ones use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
58dbf75885
Make SigSpec::is_fully_zero use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
20e64ee17b
Make is_fully_const use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
bf4cfbd72d
Make SigSpec::is_wire/is_chunk/is_fully_const use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
fd7b4f4a8b
Make SigSpec::updhash() use chunk iterator
2025-10-31 11:53:38 +00:00
Robert O'Callahan
37e4c2e8f8
Make SigSpec::chunks() return an object that can be iterated over without packing the SigSpec
2025-10-31 11:53:38 +00:00
Robert O'Callahan
c4f3e61339
Make Module stop accessing internals of SigSpec
2025-10-29 18:32:10 +00:00
Emil J
c9a4c608ce
Merge pull request #5446 from rocallahan/avoid-moved-from
...
Don't recompute hash using moved-out-of value
2025-10-29 16:16:57 +01:00
Miodrag Milanović
7f6ea39507
Merge pull request #5449 from yrabbit/adc-5
...
Gowin. Fix GW5A ADCs.
2025-10-29 11:11:47 +01:00
YRabbit
2a3720921c
Gowin. Fix GW5A ADCs.
...
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-29 12:48:21 +10:00
github-actions[bot]
75eff54b31
Bump version
2025-10-29 00:24:43 +00:00
Miodrag Milanović
3b9f06c130
Merge pull request #5447 from pu-cc/gatemate-fix-serdes-cdr
...
gatemate: fix SERDES CDR parameters
2025-10-28 09:54:13 +01:00
Robert O'Callahan
a27b1a83ae
Don't recompute hash using moved-out-of value
2025-10-28 07:41:10 +00:00
Patrick Urban
14c1802b01
gatemate: fix SERDES CDR parameters
2025-10-27 15:47:48 +01:00
github-actions[bot]
8bc63ef6da
Bump version
2025-10-26 00:25:16 +00:00
YRabbit
3956f103a9
Gowin. Handle the WRITE_MODE.
...
Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-25 23:15:23 +01:00
github-actions[bot]
f5c9e122de
Bump version
2025-10-24 00:21:47 +00:00
YRabbit
64700dec65
Gowin. Disable unsupported BSRAM mode in GW5A
...
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-23 09:59:56 +01:00
Miodrag Milanović
2613c1c0a9
Merge pull request #5438 from cr1901/posix-bugpoint
...
Add sys/wait.h header to bugpoint to bring in constants.
2025-10-22 12:40:26 +02:00
github-actions[bot]
37875fdedf
Bump version
2025-10-21 00:23:46 +00:00
William D. Jones
311a2739f6
Add sys/wait.h header to bugpoint to bring in constants.
2025-10-20 19:50:18 -04:00
Jannis Harder
f6fb423ee8
Merge pull request #5430 from YosysHQ/micko/sim_cycle_width
...
sim: Make cycle width small as possible and configurable
2025-10-20 18:51:32 +02:00
Jannis Harder
6a0ee6e4fb
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
github-actions[bot]
1598771a37
Bump version
2025-10-19 00:26:17 +00:00
Mohamed Gaber
b510c36162
hotfix: headers mistakenly added to clean target
...
- fix `make clean` deleting a number of headers when ENABLE_PYOSYS is set to 1
2025-10-18 14:08:20 +01:00
github-actions[bot]
272aa9cde2
Bump version
2025-10-17 00:23:40 +00:00
Maxim Kudinov
6535995005
synth_gowin: fix help hint style
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8c347826f6
synth_gowin: make help description more clear
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8f6d63c082
synth_gowin: make setundef an off by default option
2025-10-16 11:09:28 +01:00
Miodrag Milanovic
f11a61b32b
sim: Make cycle width small as possible and configurable
2025-10-16 11:37:44 +02:00
Miodrag Milanovic
db8c1878a0
fix dlopen using fs:path with mingw
2025-10-16 08:30:43 +02:00
