mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 13:07:58 +00:00
Make SigSpec::is_fully_undef use chunk iterator
This commit is contained in:
parent
b2de56cae2
commit
5c8f9f14ca
1 changed files with 4 additions and 5 deletions
|
|
@ -5484,12 +5484,11 @@ bool RTLIL::SigSpec::is_fully_undef() const
|
|||
{
|
||||
cover("kernel.rtlil.sigspec.is_fully_undef");
|
||||
|
||||
pack();
|
||||
for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
|
||||
if (it->width > 0 && it->wire != NULL)
|
||||
for (auto &chunk : chunks()) {
|
||||
if (chunk.width > 0 && chunk.wire != NULL)
|
||||
return false;
|
||||
for (size_t i = 0; i < it->data.size(); i++)
|
||||
if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
|
||||
for (RTLIL::State d : chunk.data)
|
||||
if (d != RTLIL::State::Sx && d != RTLIL::State::Sz)
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue