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Add try_as_const and use the const iterator a bit more
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parent
04a6dbc562
commit
000c081965
2 changed files with 29 additions and 11 deletions
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@ -5621,33 +5621,48 @@ std::string RTLIL::SigSpec::as_string() const
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return str;
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}
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std::optional<RTLIL::Const> RTLIL::SigSpec::try_as_const() const
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{
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cover("kernel.rtlil.sigspec.as_const");
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auto it = chunks().begin();
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if (it == chunks().end())
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return RTLIL::Const();
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SigChunk chunk = *it;
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if (chunk.wire != NULL || ++it != chunks().end())
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return std::nullopt;
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return RTLIL::Const(std::move(chunk.data));
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}
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RTLIL::Const RTLIL::SigSpec::as_const() const
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{
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cover("kernel.rtlil.sigspec.as_const");
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pack();
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log_assert(is_fully_const() && GetSize(chunks_) <= 1);
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if (width_)
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return chunks_[0].data;
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return RTLIL::Const();
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std::optional<RTLIL::Const> c = try_as_const();
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log_assert(c.has_value());
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return *c;
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}
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RTLIL::Wire *RTLIL::SigSpec::as_wire() const
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{
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cover("kernel.rtlil.sigspec.as_wire");
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pack();
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log_assert(is_wire());
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return chunks_[0].wire;
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auto it = chunks().begin();
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log_assert(it != chunks().end());
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RTLIL::SigChunk chunk = *it;
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log_assert(++it == chunks().end() && chunk.wire && chunk.wire->width == width_);
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return chunk.wire;
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}
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RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
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{
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cover("kernel.rtlil.sigspec.as_chunk");
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pack();
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log_assert(is_chunk());
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return chunks_[0];
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auto it = chunks().begin();
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log_assert(it != chunks().end());
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RTLIL::SigChunk chunk = *it;
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log_assert(++it == chunks().end());
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return chunk;
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}
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RTLIL::SigBit RTLIL::SigSpec::as_bit() const
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@ -1453,6 +1453,9 @@ public:
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int as_int_saturating(bool is_signed = false) const;
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std::string as_string() const;
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// Returns std::nullopt if there are any non-constant bits. Returns an empty
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// Const if this has zero width.
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std::optional<RTLIL::Const> try_as_const() const;
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RTLIL::Const as_const() const;
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RTLIL::Wire *as_wire() const;
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RTLIL::SigChunk as_chunk() const;
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