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https://github.com/YosysHQ/yosys
synced 2025-11-03 13:07:58 +00:00
Don't reset the hash when unpacking, instead clear the hash whenever bits are modified
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parent
a1f7d6c9bf
commit
ab525643a7
2 changed files with 20 additions and 3 deletions
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@ -4725,7 +4725,6 @@ void RTLIL::SigSpec::unpack() const
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that->bits_.emplace_back(c, i);
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that->chunks_.clear();
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that->hash_ = 0;
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}
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void RTLIL::SigSpec::updhash() const
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@ -4757,6 +4756,7 @@ void RTLIL::SigSpec::sort()
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unpack();
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cover("kernel.rtlil.sigspec.sort");
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std::sort(bits_.begin(), bits_.end());
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hash_ = 0;
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}
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void RTLIL::SigSpec::sort_and_unify()
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@ -4773,6 +4773,7 @@ void RTLIL::SigSpec::sort_and_unify()
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unique_bits.erase(last, unique_bits.end());
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*this = unique_bits;
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hash_ = 0;
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}
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
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@ -4804,6 +4805,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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other->bits_[j] = with.bits_[it->second];
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}
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}
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other->hash_ = 0;
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other->check();
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}
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@ -4829,6 +4831,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
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if (it != rules.end())
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other->bits_[i] = it->second;
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}
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other->hash_ = 0;
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other->check();
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}
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@ -4854,6 +4857,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
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if (it != rules.end())
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other->bits_[i] = it->second;
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}
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other->hash_ = 0;
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other->check();
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}
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@ -4880,6 +4884,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
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if (other != NULL) {
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log_assert(size() == other->size());
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other->unpack();
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other->hash_ = 0;
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--)
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@ -4899,6 +4904,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
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break;
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}
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}
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hash_ = 0;
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check();
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}
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@ -4926,6 +4932,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
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if (other != NULL) {
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log_assert(size() == other->size());
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other->unpack();
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other->hash_ = 0;
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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@ -4938,6 +4945,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
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}
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}
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}
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hash_ = 0;
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check();
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}
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@ -4954,6 +4962,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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if (other != NULL) {
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log_assert(size() == other->size());
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other->unpack();
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other->hash_ = 0;
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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@ -4966,6 +4975,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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}
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}
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}
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hash_ = 0;
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check();
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}
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@ -4982,6 +4992,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
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if (other != NULL) {
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log_assert(size() == other->size());
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other->unpack();
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other->hash_ = 0;
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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@ -4994,6 +5005,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
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}
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}
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}
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hash_ = 0;
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check();
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}
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@ -5081,6 +5093,7 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
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bits_.at(offset + i) = bit;
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++i;
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}
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hash_ = 0;
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check();
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}
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@ -5124,6 +5137,7 @@ void RTLIL::SigSpec::remove_const()
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width_ = bits_.size();
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}
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hash_ = 0;
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check();
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}
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@ -5140,6 +5154,7 @@ void RTLIL::SigSpec::remove(int offset, int length)
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bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
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width_ = bits_.size();
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hash_ = 0;
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check();
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}
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@ -5186,6 +5201,7 @@ void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewri
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for (RTLIL::SigChunk &chunk : chunks_)
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if (chunk.wire != nullptr)
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rewrite(chunk.wire);
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hash_ = 0;
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}
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void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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@ -5221,6 +5237,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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}
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width_ += signal.size();
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hash_ = 0;
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check();
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}
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@ -5252,6 +5269,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
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}
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width_++;
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hash_ = 0;
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check();
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}
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@ -5269,7 +5287,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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while (size() < width)
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append(padding);
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}
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}
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RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
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@ -1365,7 +1365,7 @@ public:
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inline int size() const { return width_; }
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inline bool empty() const { return size() == 0; }
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inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }
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inline RTLIL::SigBit &operator[](int index) { inline_unpack(); hash_ = 0; return bits_.at(index); }
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inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }
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inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
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