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Make SigSpec::is_wire/is_chunk/is_fully_const use chunk iterator

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This commit is contained in:
Robert O'Callahan 2025-10-28 12:36:12 +00:00
parent fd7b4f4a8b
commit bf4cfbd72d
1 changed files with 12 additions and 6 deletions
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18
kernel/rtlil.cc
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@ -5401,22 +5401,28 @@ bool RTLIL::SigSpec::is_wire() const
{
cover("kernel.rtlil.sigspec.is_wire");
pack();
return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
Chunks cs = chunks();
auto it = cs.begin();
if (it == cs.end())
return false;
const RTLIL::SigChunk &chunk = *it;
return chunk.wire && chunk.wire->width == width_ && ++it == cs.end();
}
bool RTLIL::SigSpec::is_chunk() const
{
cover("kernel.rtlil.sigspec.is_chunk");
pack();
return GetSize(chunks_) == 1;
Chunks cs = chunks();
auto it = cs.begin();
if (it == cs.end())
return false;
return ++it == cs.end();
}
bool RTLIL::SigSpec::known_driver() const
{
pack();
for (auto &chunk : chunks_)
for (auto &chunk : chunks())
if (chunk.is_wire() && !chunk.wire->known_driver())
return false;
return true;