3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 13:07:58 +00:00

Make SigSpec conversion to vector of SigChunk use chunks iterator

This commit is contained in:
Robert O'Callahan 2025-10-30 10:30:03 +00:00
parent 4672127610
commit 8c9dd3209a
2 changed files with 9 additions and 1 deletions

View file

@ -5899,6 +5899,14 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
return true;
}
RTLIL::SigSpec::operator std::vector<RTLIL::SigChunk>() const
{
std::vector<RTLIL::SigChunk> result;
for (const RTLIL::SigChunk &c : chunks())
result.push_back(c);
return result;
}
RTLIL::CaseRule::~CaseRule()
{
for (auto it = switches.begin(); it != switches.end(); it++)

View file

@ -1473,7 +1473,7 @@ public:
static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
operator std::vector<RTLIL::SigChunk>() const { pack(); return chunks_; }
operator std::vector<RTLIL::SigChunk>() const;
operator std::vector<RTLIL::SigBit>() const { return bits(); }
const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }