236 commits

Author	SHA1	Message	Date
Clifford Wolf	cdd6e11af5	Added support for blanks after -I and -D in read_verilog	2014-02-02 13:06:21 +01:00
Clifford Wolf	af325bf206	Fixed comment/eol parsing in ilang frontend	2014-02-01 17:28:02 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	88fbdd4916	Fixed algorithmic complexity of AST simplification of long expressions	2014-01-20 20:25:20 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	13359d65ba	Fixed parsing of verilog macros at end of line	2014-01-18 19:22:20 +01:00
Clifford Wolf	6170cfe9cd	Added verilog_defaults command	2014-01-17 17:22:29 +01:00
Clifford Wolf	a3d94bf888	Fixed typo in frontends/ast/simplify.cc	2014-01-12 21:04:42 +01:00
Clifford Wolf	8f11eaaca6	Added updating of RTLIL::autoidx to ilang frontend	2014-01-03 17:51:05 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	364f277afb	Fixed a stupid access after delete bug	2013-12-29 20:18:22 +01:00
Clifford Wolf	1dcbba1abf	Fixed parsing of non-arg macro calls followed by "("	2013-12-27 16:25:27 +01:00
Clifford Wolf	72026a934e	Fixed parsing of macros with no arguments and expansion text starting with "("	2013-12-27 15:05:52 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	891e4b5b0d	Keep strings as strings in const ternary and concat	2013-12-05 13:26:17 +01:00
Clifford Wolf	e935bb6eda	Added const folding support for $signed and $unsigned	2013-12-05 13:09:41 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	853538d78b	Fixed generate-for (and disabled double warning for auto-wire)	2013-12-04 21:33:00 +01:00
Clifford Wolf	3c220e0b32	Added support for $clog2 system function	2013-12-04 21:19:54 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	507c63d112	Added support for local regs in named blocks	2013-12-04 09:10:16 +01:00
Clifford Wolf	10aa08dca1	Fixed temp net name generation in rtlil process generator for abbreviated name matching	2013-11-28 21:47:08 +01:00
Clifford Wolf	0e52f3fa01	Added "src" attribute to processes	2013-11-28 17:37:50 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	95c94a02fc	Fixed async proc detection in mem2reg	2013-11-21 21:26:56 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	08ceb3729e	Fixed ilang parser: memory width	2013-11-20 19:55:52 +01:00
Clifford Wolf	65ad556f3d	Another name resolution bugfix for generate blocks	2013-11-20 13:57:40 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	c4c299eb5a	Do not allow memory bit select on the left side of an assignment	2013-11-20 12:18:46 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys|synthesis) comment support	2013-11-20 11:44:09 +01:00
Clifford Wolf	ac2be2d892	Fixed name resolution of local tasks and functions in generate block	2013-11-20 11:05:58 +01:00