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Implemented correct handling of signed module parameters
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parent
1e6836933d
commit
609caa23b5
8 changed files with 19 additions and 8 deletions
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@ -792,7 +792,7 @@ AstModule::~AstModule()
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}
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// create a new parametric module (when needed) and return the name of the generated module
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters)
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{
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log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
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@ -826,7 +826,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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rewrite_parameter:
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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delete child->children.at(0);
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child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, child->is_signed);
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child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, signed_parameters.count(para_id) > 0);
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hash_data.insert(hash_data.end(), child->str.begin(), child->str.end());
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hash_data.push_back(0);
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hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end());
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@ -227,7 +227,7 @@ namespace AST
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AstNode *ast;
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bool nolatches, nomem2reg, mem2reg, lib, noopt;
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virtual ~AstModule();
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virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
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virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters);
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virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
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virtual RTLIL::Module *clone() const;
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};
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@ -1309,9 +1309,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (child->str.size() == 0) {
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char buf[100];
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snprintf(buf, 100, "$%d", ++para_counter);
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if (child->children[0]->is_signed)
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cell->signed_parameters.insert(buf);
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cell->parameters[buf].str = child->children[0]->str;
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cell->parameters[buf].bits = child->children[0]->bits;
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} else {
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if (child->children[0]->is_signed)
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cell->signed_parameters.insert(child->str);
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cell->parameters[child->str].str = child->children[0]->str;
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cell->parameters[child->str].bits = child->children[0]->bits;
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}
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