3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 01:55:33 +00:00

Added correct handling of $memwr priority

This commit is contained in:
Clifford Wolf 2014-01-03 00:22:17 +01:00
parent 536e20bde1
commit fb2bf934dc
5 changed files with 42 additions and 2 deletions

View file

@ -1271,6 +1271,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1);
}
break;