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Renamed "placeholder" to "blackbox"

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This commit is contained in:
Clifford Wolf 2013-11-22 15:01:12 +01:00
parent c854ad2e7e
commit 295e352ba6
12 changed files with 27 additions and 27 deletions
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2
frontends/ast/ast.cc
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@ -720,7 +720,7 @@ static AstModule* process_module(AstNode *ast)
delete child;
}
ast->children.swap(new_children);
ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
}
ignoreThisSignalsInInitial = RTLIL::SigSpec();

2
frontends/verilog/verilog_frontend.cc
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@ -90,7 +90,7 @@ struct VerilogFrontend : public Frontend {
log(" do not run the pre-processor\n");
log("\n");
log(" -lib\n");
log(" only create empty placeholder modules\n");
log(" only create empty blackbox modules\n");
log("\n");
log(" -noopt\n");
log(" don't perform basic optimizations (such as const folding) in the\n");