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Code Activity
yosys/frontends
History
Clifford Wolf a362fd81ae Fixed O(n^2) performance bug in verilog preprocessor
2013-11-22 14:08:43 +01:00
..
ast Fixed async proc detection in mem2reg 2013-11-21 21:26:56 +01:00
ilang Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
verilog Fixed O(n^2) performance bug in verilog preprocessor 2013-11-22 14:08:43 +01:00