nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
nella
362e828dc2
Simplify check -latchonly calls in synth.
2026-07-07 10:10:00 +02:00
nella
a3b8609c84
Add -nolatches check option.
2026-06-24 10:38:10 +02:00
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a
End of file fix
2026-06-23 07:23:41 +02:00
nella
b3b1394cf1
Fixup level policy.
2026-06-18 18:00:51 +02:00
nella
32a268d745
Emit errors before dfflegalize.
2026-06-18 17:07:24 +02:00
nella
b2d688dbf9
Error out on latches.
2026-06-17 17:36:32 +02:00
nella
c814ef35e3
Emit latch warning.
2026-06-17 11:27:43 +02:00
Catherine
a727e7f6e7
Migrate build system to CMake
...
See #5895 for details.
This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
nella
1414012676
Add sign and op checks.
2026-05-28 09:58:18 +02:00
nella
7fef67a141
Simplify nexus map.
2026-05-28 09:58:18 +02:00
nella
d6106f141c
Add matching for fused mac operations for Nexus ( fix #5906 ).
2026-05-28 09:58:18 +02:00
Codexplorer
e41b969da2
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
nella
fff034d2f8
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
Krystine Sherwin
c3ffb48a6b
Add and use fix_mod.py
2026-01-28 07:45:58 +13:00
Miodrag Milanovic
714603bf69
synth_nexus to synth_lattice
2025-09-26 19:45:03 +01:00
Miodrag Milanovic
58f9531bfb
enable ABC9 by default except for XO2/3/3D
2025-09-25 15:44:05 +01:00
Miodrag Milanović
4b9e4bfae9
Update techlibs/lattice/synth_lattice.cc
...
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
faf82a5ff5
Add help message for synth_ecp5
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
47a2215fe0
Update filenames and location for test script
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
4a7f94f1c1
Enable synth_ecp5 wrapper and copy sim files for backwards compatibility
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
e7ac237499
Delete synth_ecp5
2025-09-25 15:44:03 +01:00
Miodrag Milanovic
cfe53b7395
Move diamond tests
2025-09-25 15:38:57 +01:00
Miodrag Milanovic
b94b39cd40
Special DP16KD model is required
2025-09-25 15:38:55 +01:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
David Anderson
af8e85b7d2
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
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prjtrellis documentation shows that EBR clock inputs have optional inverters.
The bram techmap outputs those parameters, and nextpnr consumes them. But for
whatever reason, Diamond doesn't include those parameters in its blackbox
models. This makes synth_lattice fail when targeting ECP5 with a design that
maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions.
This change fixes up the ECP5 bram blackbox models at generation time, by
adding the missing parameters back in.
Signed-off-by: David Anderson <dave@natulte.net>
2025-04-21 11:57:49 -07:00
Krystine Sherwin
ff10aeebd6
Fix some synth_* help messages
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Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`.
Also fix `map_iopad` section being empty in `synth_fabulous`.
2024-03-18 11:33:18 +13:00
Martin Povišer
c028f25158
lattice: Disable broken port configuration in bram inference
2023-12-21 10:47:40 +01:00
Martin Povišer
fc5c5172f8
lattice: Fix mapping onto DP8KC for data width 1 or 2
2023-12-20 23:42:12 +01:00
Martin Povišer
de16cd253d
synth_lattice: Enable booth by default on XO3
2023-11-22 15:47:11 +01:00
N. Engelhardt
52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work
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MachXO3 QoR improvements
2023-11-13 16:56:06 +01:00
Martin Povišer
3ffa4b5e5d
synth_lattice: Wire up cmp2softlogic as an option
2023-11-13 10:42:12 +01:00
Martin Povišer
fed2720999
synth_lattice: Optimize flip-flop memories better
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After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
2023-11-07 16:29:56 +01:00
Martin Povišer
ee3a4ce14d
synth_lattice: Merge NOT gates on DFF control signals
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`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
2023-11-07 16:21:39 +01:00
Miodrag Milanovic
72bec94ef4
Add missing file for XO3D
2023-09-01 10:15:51 +02:00
Miodrag Milanovic
792cf8326e
defult nowidelut for xo2/3/3d
2023-08-29 10:08:55 +02:00
Miodrag Milanovic
b168ff99d0
fix generated blackboxes for ecp5
2023-08-28 16:26:26 +02:00
Miodrag Milanovic
0756285710
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
Miodrag Milanovic
3b9ebfa672
Addressed code review comments
2023-08-25 11:10:20 +02:00
Miodrag Milanovic
541c1ab567
add script for blackbox extraction
2023-08-23 11:51:00 +02:00
Miodrag Milanovic
e3c15f003e
Create synth_lattice
2023-08-23 10:53:21 +02:00
Miodrag Milanovic
a8809989c4
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
