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https://github.com/YosysHQ/yosys
synced 2026-05-28 21:06:33 +00:00
Add sign and op checks.
This commit is contained in:
nella
nella
parent
7fef67a141
commit
1414012676
1 changed files with 109 additions and 66 deletions
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@ -15,21 +15,35 @@ match add
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endmatch
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code
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SigSpec mul_out = port(mul, \Y);
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IdString add_AB;
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18");
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IdString add_C = (add_AB == \A) ? \B : \A;
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if (mul->getParam(\A_SIGNED).as_bool() != mul->getParam(\B_SIGNED).as_bool()) {
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reject;
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}
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mac->setPort(\A, port(mul, \A));
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mac->setPort(\B, port(mul, \B));
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mac->setPort(\C, port(add, add_C));
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mac->setPort(\Y, port(add, \Y));
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mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
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mac->setParam(\B_SIGNED, mul->getParam(\B_SIGNED));
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mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
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{
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SigSpec mul_out = port(mul, \Y);
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IdString add_AB;
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autoremove(mul);
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autoremove(add);
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if (GetSize(port(add, \A)) >= GetSize(mul_out) && port(add, \A).extract(0, GetSize(mul_out)) == mul_out) {
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add_AB = \A;
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} else if (GetSize(port(add, \B)) >= GetSize(mul_out) && port(add, \B).extract(0, GetSize(mul_out)) == mul_out) {
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add_AB = \B;
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} else {
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reject;
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}
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18");
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IdString add_C = (add_AB == \A) ? \B : \A;
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mac->setPort(\A, port(mul, \A));
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mac->setPort(\B, port(mul, \B));
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mac->setPort(\C, port(add, add_C));
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mac->setPort(\Y, port(add, \Y));
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mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
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mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
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autoremove(mul);
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autoremove(add);
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}
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accept;
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endcode
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@ -57,41 +71,53 @@ endmatch
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code
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SigSpec preadd_out = port(preadd, \Y);
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IdString actual_mul_AB;
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Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18");
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IdString mul_other = (actual_mul_AB == \A) ? \B : \A;
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IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
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IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
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SigSpec sig_A = port(preadd, \A);
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SigSpec sig_C = port(preadd, \B);
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SigSpec sig_B = port(mul, mul_other);
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sig_A.extend_u0(18, false);
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sig_C.extend_u0(18, false);
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sig_B.extend_u0(18, false);
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mac->setPort(\A, sig_A.extract(0, 18));
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mac->setPort(\C, sig_C.extract(0, 18));
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mac->setPort(\B, sig_B.extract(0, 18));
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if (pipe_ff) {
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mac->setPort(\Y, port(pipe_ff, \Q));
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mac->setPort(\CLK, port(pipe_ff, \CLK));
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mac->setParam(\PIPELINED, State::S1);
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if (GetSize(port(mul, \A)) >= GetSize(preadd_out) && port(mul, \A).extract(0, GetSize(preadd_out)) == preadd_out) {
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actual_mul_AB = \A;
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} else if (GetSize(port(mul, \B)) >= GetSize(preadd_out) && port(mul, \B).extract(0, GetSize(preadd_out)) == preadd_out) {
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actual_mul_AB = \B;
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} else {
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mac->setPort(\Y, port(mul, \Y));
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mac->setPort(\CLK, State::S0);
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mac->setParam(\PIPELINED, State::S0);
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reject;
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}
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mac->setParam(\A_SIGNED, mul->getParam(sgn_AC));
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mac->setParam(\B_SIGNED, mul->getParam(sgn_B));
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mac->setParam(\C_SIGNED, mul->getParam(sgn_AC));
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{
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Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18");
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IdString mul_other = (actual_mul_AB == \A) ? \B : \A;
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IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
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IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
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SigSpec sig_A = port(preadd, \A);
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SigSpec sig_C = port(preadd, \B);
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SigSpec sig_B = port(mul, mul_other);
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sig_A.extend_u0(18, false);
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sig_C.extend_u0(18, false);
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sig_B.extend_u0(18, false);
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mac->setPort(\A, sig_A.extract(0, 18));
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mac->setPort(\C, sig_C.extract(0, 18));
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mac->setPort(\B, sig_B.extract(0, 18));
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if (pipe_ff) {
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mac->setPort(\Y, port(pipe_ff, \Q));
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mac->setPort(\CLK, port(pipe_ff, \CLK));
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mac->setParam(\PIPELINED, State::S1);
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} else {
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mac->setPort(\Y, port(mul, \Y));
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mac->setPort(\CLK, State::S0);
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mac->setParam(\PIPELINED, State::S0);
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}
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mac->setParam(\A_SIGNED, mul->getParam(sgn_AC));
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mac->setParam(\B_SIGNED, mul->getParam(sgn_B));
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mac->setParam(\C_SIGNED, mul->getParam(sgn_AC));
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if (pipe_ff) autoremove(pipe_ff);
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autoremove(mul);
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autoremove(preadd);
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}
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if (pipe_ff) autoremove(pipe_ff);
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autoremove(mul);
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autoremove(preadd);
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accept;
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endcode
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@ -136,30 +162,47 @@ match mul0
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endmatch
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code
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
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bool is_signed = mul0->getParam(\A_SIGNED).as_bool();
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auto ext9 = [&](SigSpec s) {
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s.extend_u0(9, is_signed);
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return s;
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};
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mac->setPort(\A0, ext9(port(mul0, \A)));
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mac->setPort(\B0, ext9(port(mul0, \B)));
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mac->setPort(\A1, ext9(port(mul1, \A)));
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mac->setPort(\B1, ext9(port(mul1, \B)));
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mac->setPort(\A2, ext9(port(mul2, \A)));
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mac->setPort(\B2, ext9(port(mul2, \B)));
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mac->setPort(\A3, ext9(port(mul3, \A)));
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mac->setPort(\B3, ext9(port(mul3, \B)));
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mac->setPort(\Y, port(add_top, \Y));
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mac->setParam(\SIGNED, mul0->getParam(\A_SIGNED));
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if (
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mul0->getParam(\B_SIGNED).as_bool() != is_signed ||
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mul1->getParam(\A_SIGNED).as_bool() != is_signed ||
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mul1->getParam(\B_SIGNED).as_bool() != is_signed ||
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mul2->getParam(\A_SIGNED).as_bool() != is_signed ||
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mul2->getParam(\B_SIGNED).as_bool() != is_signed ||
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mul3->getParam(\A_SIGNED).as_bool() != is_signed ||
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mul3->getParam(\B_SIGNED).as_bool() != is_signed
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) {
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reject;
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}
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{
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
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auto ext9 = [&](SigSpec s) {
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s.extend_u0(9, is_signed);
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return s;
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};
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mac->setPort(\A0, ext9(port(mul0, \A)));
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mac->setPort(\B0, ext9(port(mul0, \B)));
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mac->setPort(\A1, ext9(port(mul1, \A)));
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mac->setPort(\B1, ext9(port(mul1, \B)));
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mac->setPort(\A2, ext9(port(mul2, \A)));
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mac->setPort(\B2, ext9(port(mul2, \B)));
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mac->setPort(\A3, ext9(port(mul3, \A)));
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mac->setPort(\B3, ext9(port(mul3, \B)));
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mac->setPort(\Y, port(add_top, \Y));
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mac->setParam(\SIGNED, is_signed ? State::S1 : State::S0);
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autoremove(add_top);
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autoremove(add_mid);
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autoremove(add_bot);
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autoremove(mul0);
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autoremove(mul1);
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autoremove(mul2);
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autoremove(mul3);
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}
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autoremove(add_top);
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autoremove(add_mid);
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autoremove(add_bot);
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autoremove(mul0);
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autoremove(mul1);
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autoremove(mul2);
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autoremove(mul3);
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accept;
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endcode
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endcode
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