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Simplify check -latchonly calls in synth.

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This commit is contained in:
nella 2026-07-07 10:10:00 +02:00
parent 6675c45e29
commit 362e828dc2
6 changed files with 6 additions and 18 deletions
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4
techlibs/efinix/synth_efinix.cc
View file

@ -203,10 +203,8 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_ffs"))
{
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");

4
techlibs/fabulous/synth_fabulous.cc
View file

@ -372,10 +372,8 @@ struct SynthPass : public ScriptPass
} else {
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
}
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v");
if (help_mode) {

4
techlibs/ice40/synth_ice40.cc
View file

@ -419,10 +419,8 @@ struct SynthIce40Pass : public ScriptPass
run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)");

4
techlibs/lattice/synth_lattice.cc
View file

@ -547,10 +547,8 @@ struct SynthLatticePass : public ScriptPass
if (abc2 || help_mode)
run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) {
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}

4
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -339,10 +339,8 @@ struct SynthNanoXplorePass : public ScriptPass
dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge");
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef");

4
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -330,10 +330,8 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");