2436 commits

Author	SHA1	Message	Date
Miodrag Milanović	9191491eed	Merge 0f1f20d0ed into 5fd39ff3e1	2026-03-20 15:37:31 +00:00
nella	57bf4378d3	Consolidated memlib generate script	2026-03-20 16:32:46 +01:00
nella	a54c0149bf	Convert bram tests	2026-03-20 16:32:46 +01:00
nella	e7cc04954d	Convert memfile tests	2026-03-20 16:32:46 +01:00
nella	ca77e0a5db	Convert memlib tests	2026-03-20 16:32:46 +01:00
Miodrag Milanovic	0297eabeb3	Make test simple	2026-03-20 16:16:58 +01:00
Miodrag Milanovic	323747e3de	Better fix	2026-03-20 15:38:24 +01:00
Miodrag Milanovic	4ff4af7389	Try fixing tests	2026-03-20 15:12:51 +01:00
Miodrag Milanovic	799c07a126	Did share, opt_share and fsm	2026-03-20 12:47:15 +01:00
Emil J	9746bd3897	Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection ... setundef: respect selection for cells, processes, and connections	2026-03-18 22:53:06 +00:00
Lofty	c4cc53a72e	synth: fix after abc -fast removal	2026-03-18 17:59:58 +01:00
Miodrag Milanovic	2b10385edd	Convert xprop tests	2026-03-18 15:25:28 +01:00
Miodrag Milanovic	de8b6286b8	Converted some more	2026-03-18 09:54:33 +01:00
Miodrag Milanovic	d0ac6d9791	Converted blif tests	2026-03-18 09:45:33 +01:00
Miodrag Milanovic	92bdccf2be	Convert memories tests	2026-03-18 08:46:58 +01:00
Miodrag Milanovic	77147fb0db	Correctly handle errors	2026-03-18 08:46:34 +01:00
Miodrag Milanovic	fa92d22660	Document not covered	2026-03-16 15:45:59 +01:00
Miodrag Milanovic	488f144245	Convert autotest script wrapper	2026-03-16 13:07:11 +01:00
Emil J	c8f715fed8	Merge pull request #5664 from rocallahan/parallel-opt-clean ... Parallelize `opt_clean` pass	2026-03-16 09:52:34 +00:00
Miodrag Milanovic	896fac04ed	cleanup	2026-03-16 10:48:10 +01:00
Miodrag Milanovic	af3a53720c	Use generic testing on few more places	2026-03-16 10:13:10 +01:00
Miodrag Milanovic	80fff7ce09	cleanup	2026-03-13 11:18:03 +01:00
Miodrag Milanovic	f2e1ac23a2	add prep	2026-03-13 11:15:21 +01:00
Miodrag Milanovic	413b9a4639	Add common.mk	2026-03-13 11:00:08 +01:00
Miodrag Milanovic	144da16583	report on summary	2026-03-13 10:15:17 +01:00
Miodrag Milanovic	903c74e42b	Look for all result files	2026-03-13 10:10:34 +01:00
Miodrag Milanovic	f9cd49f7b9	Save results, and create summary and report	2026-03-13 09:51:15 +01:00
Miodrag Milanovic	2fb0ca49ff	Convert gen-tests shell script to python	2026-03-13 08:38:05 +01:00
Miodrag Milanovic	486c3715fb	Enabled realmath that was disabled for some reason	2026-03-11 08:02:11 +01:00
Miodrag Milanovic	2123121d23	Fix deprecation warning	2026-03-10 16:15:07 +01:00
Miodrag Milanovic	8a6954413f	Clean some seed-tests outputs	2026-03-10 15:57:24 +01:00
Miodrag Milanovic	ede782d7e3	Clean some seed-tests outputs	2026-03-10 11:50:30 +01:00
Miodrag Milanovic	a155994868	Cleanup for abcopt-tests	2026-03-10 11:18:05 +01:00
Miodrag Milanovic	169b9994dc	Ignore some generated files	2026-03-10 11:05:47 +01:00
Miodrag Milanovic	c08a2aa3ff	Do not write to console for makefile-tests	2026-03-10 11:02:20 +01:00
Miodrag Milanovic	1a864c72ae	Make sure targets are built for tests	2026-03-10 10:08:52 +01:00
Miodrag Milanovic	108a9133d0	Move clean for tests in proper Makefile	2026-03-10 10:01:23 +01:00
Miodrag Milanovic	92ef719434	Split vanilla-test to separate Makefile	2026-03-10 09:41:39 +01:00
abhinavputhran	314d01b35f	changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change	2026-03-08 20:14:03 -04:00
abhinavputhran	47c2257f82	setundef: more tests! and wire selection in -init mode	2026-03-08 19:41:31 -04:00
abhinavputhran	c23ba3f917	I think CI runs within the tests directory based on error so I changed the file path	2026-03-08 18:15:35 -04:00
abhinavputhran	5048dac854	setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer	2026-03-06 18:12:03 -05:00
Lofty	050483a6b2	Merge pull request #5698 from YosysHQ/lofty/analogdevices ... synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]	2026-03-06 08:57:59 +00:00
Miodrag Milanovic	602f3fd1a5	Add missing EOL	2026-03-06 09:10:55 +01:00
Miodrag Milanovic	52533b0d1c	Update opt_lut_ins and stat for analogdevices and remove ecp5	2026-03-06 09:10:36 +01:00
Robert O'Callahan	1260fda83a	Add 'init' attributes to RTLIL fuzzing	2026-03-06 02:20:08 +00:00
Robert O'Callahan	cdfc586f18	Add unit tests for ConcurrentWorkQueue	2026-03-06 02:20:08 +00:00
Robert O'Callahan	1e96328ede	Add some tests for ShardedHashSet	2026-03-06 02:20:08 +00:00
Robert O'Callahan	3910d569da	Add unit tests for ConcurrentQueue and ThreadPool	2026-03-06 02:20:08 +00:00
Robert O'Callahan	ac55935a68	Add unit-tests for ParallelDispatchThread and friends	2026-03-06 02:20:08 +00:00