1209 commits

Author	SHA1	Message	Date
Clifford Wolf	a7c6b37abf	Added "kernel/yosys.h" and "kernel/yosys.cc"	2014-07-30 14:10:15 +02:00
Clifford Wolf	273383692a	Added "test_cell" command	2014-07-29 22:07:41 +02:00
Clifford Wolf	e6df25bf74	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	2014-07-29 21:12:50 +02:00
Clifford Wolf	03c96f9ce7	Added "techmap -map %{design-name}"	2014-07-29 16:35:13 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	d86a25f145	Added std::initializer_list<> constructor to SigSpec	2014-07-28 10:52:58 +02:00
Clifford Wolf	f99495a895	Added cover() to all SigSpec constructors	2014-07-28 10:52:30 +02:00
Clifford Wolf	c4bdba78cb	Added proper Design->addModule interface	2014-07-27 21:12:09 +02:00
Clifford Wolf	5da343b7de	Added topological sorting to techmap	2014-07-27 16:43:39 +02:00
Clifford Wolf	0c86d6106c	Added SigPool::check(bit)	2014-07-27 15:38:02 +02:00
Clifford Wolf	ddd31a0b66	Small improvements in PerformanceTimer API	2014-07-27 15:14:02 +02:00
Clifford Wolf	d07a871d35	Improved performance of opt_const on large modules	2014-07-27 14:50:25 +02:00
Clifford Wolf	4be645860b	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	2014-07-27 14:47:48 +02:00
Clifford Wolf	cbc3a46a97	Added RTLIL::SigSpecConstIterator	2014-07-27 14:47:23 +02:00
Clifford Wolf	d878fcbdc7	Added log_cmd_error_expection	2014-07-27 12:05:50 +02:00
Clifford Wolf	675cb93da9	Added RTLIL::Module::wire(id) and cell(id) lookup functions	2014-07-27 11:18:31 +02:00
Clifford Wolf	0bd8fafbd2	Added RTLIL::Design::modules()	2014-07-27 11:18:30 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	d088854b47	Added conversion from ObjRange to std::vector and std::set	2014-07-27 11:18:30 +02:00
Clifford Wolf	1c8fdaeef8	Added RTLIL::ObjIterator and RTLIL::ObjRange	2014-07-27 11:18:30 +02:00
Clifford Wolf	ddc5b41848	Using std::move() in SigSpec move constructor	2014-07-27 09:20:59 +02:00
Clifford Wolf	7f3dc86ecd	Added RTLIL::SigSpec move constructor and move assignment operator	2014-07-27 02:11:57 +02:00
Clifford Wolf	c91570bde3	Mostly cosmetic changes to rtlil.h	2014-07-27 02:00:04 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	267c615640	Added support for here documents	2014-07-26 17:21:40 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cd6574ecf6	Added some missing "const" in rtlil.h	2014-07-26 15:58:22 +02:00
Clifford Wolf	7ac9dc7f6e	Added RTLIL::Module::connections()	2014-07-26 15:58:21 +02:00
Clifford Wolf	b03aec6e32	Added RTLIL::Module::connect(const RTLIL::SigSig&)	2014-07-26 14:31:47 +02:00
Clifford Wolf	3719281ed4	Automatically pack SigSpec on copy/assign	2014-07-26 13:59:30 +02:00
Clifford Wolf	e75e495c2b	Added new RTLIL::Cell port access methods	2014-07-26 12:22:58 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	4755e14e7b	Added copy-constructor-like module->addCell(name, other) method	2014-07-26 00:38:44 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	c762050e7f	Added RTLIL::SigSpec is_chunk()/as_chunk() API	2014-07-25 14:23:10 +02:00
Clifford Wolf	c4e4f79a2a	Disabled cover() for non-linux builds	2014-07-25 12:27:36 +02:00
Clifford Wolf	7f1789ad1b	Fixed typo in cover id	2014-07-25 03:41:53 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	10d2402e2f	Added cover_list() API	2014-07-24 20:47:18 +02:00
Clifford Wolf	2f54345cff	Added "cover" command	2014-07-24 16:14:19 +02:00
Clifford Wolf	e589289df7	Some improvements in SigSpec packing/unpacking and checking	2014-07-24 15:05:41 +02:00
Clifford Wolf	7679000673	Now using a dedicated ELF section for all coverage counters	2014-07-24 15:05:05 +02:00
Clifford Wolf	22ede43b3f	Small changes regarding cover() and check() in SigSpec	2014-07-24 04:46:36 +02:00